drm/bridge: tc358767: Add descriptions to register definitions

Use the register names from the datasheet. No functional change intended.

Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Reviewed-by: Robert Foss <rfoss@kernel.org>
Signed-off-by: Robert Foss <rfoss@kernel.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20231212075257.75084-8-alexander.stein@ew.tq-group.com

diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
index 10465398d4e650fedea564875a21c657c30b27f6..eb0d82a91cb9544b853f9e120c4750b3ead56243 100644 (file)
--- a/drivers/gpu/drm/bridge/tc358767.c
+++ b/drivers/gpu/drm/bridge/tc358767.c
@@ -145,10 +145,10 @@
 #define VFUEN                          BIT(0)   /* Video Frame Timing Upload */
 
 /* System */
-#define TC_IDREG               0x0500
-#define SYSSTAT                        0x0508
-#define SYSRSTENB              0x050c
+#define TC_IDREG               0x0500  /* Chip ID and Revision ID */
 #define SYSBOOT                        0x0504  /* System BootStrap Status Register */
+#define SYSSTAT                        0x0508  /* System Status Register */
+#define SYSRSTENB              0x050c /* System Reset/Enable Register */
 #define ENBI2C                         (1 << 0)
 #define ENBLCD0                                (1 << 2)
 #define ENBBM                          (1 << 3)
@@ -162,12 +162,12 @@
 #define DP0_VIDSRC_DSI_RX              (1 << 0)
 #define DP0_VIDSRC_DPI_RX              (2 << 0)
 #define DP0_VIDSRC_COLOR_BAR           (3 << 0)
-#define GPIOM                  0x0540
-#define GPIOC                  0x0544
-#define GPIOO                  0x0548
-#define GPIOI                  0x054c
-#define INTCTL_G               0x0560
-#define INTSTS_G               0x0564
+#define GPIOM                  0x0540  /* GPIO Mode Control Register */
+#define GPIOC                  0x0544  /* GPIO Direction Control Register */
+#define GPIOO                  0x0548  /* GPIO Output Register */
+#define GPIOI                  0x054c  /* GPIO Input Register */
+#define INTCTL_G               0x0560  /* General Interrupts Control Register */
+#define INTSTS_G               0x0564  /* General Interrupts Status Register */
 
 #define INT_SYSERR             BIT(16)
 #define INT_GPIO_H(x)          (1 << (x == 0 ? 2 : 10))
@@ -176,8 +176,8 @@
 #define TEST_INT_C             0x0570  /* Test Interrupts Control Register */
 #define TEST_INT_S             0x0574  /* Test Interrupts Status Register */
 
-#define INT_GP0_LCNT           0x0584
-#define INT_GP1_LCNT           0x0588
+#define INT_GP0_LCNT           0x0584  /* Interrupt GPIO0 Low Count Value Register */
+#define INT_GP1_LCNT           0x0588  /* Interrupt GPIO1 Low Count Value Register */
 
 /* Control */
 #define DP0CTL                 0x0600
@@ -187,9 +187,9 @@
 #define DP_EN                          BIT(0)   /* Enable DPTX function */
 
 /* Clocks */
-#define DP0_VIDMNGEN0          0x0610
-#define DP0_VIDMNGEN1          0x0614
-#define DP0_VMNGENSTATUS       0x0618
+#define DP0_VIDMNGEN0          0x0610  /* DP0 Video Force M Value Register */
+#define DP0_VIDMNGEN1          0x0614  /* DP0 Video Force N Value Register */
+#define DP0_VMNGENSTATUS       0x0618  /* DP0 Video Current M Value Register */
 #define DP0_AUDMNGEN0          0x0628  /* DP0 Audio Force M Value Register */
 #define DP0_AUDMNGEN1          0x062c  /* DP0 Audio Force N Value Register */
 #define DP0_AMNGENSTATUS       0x0630  /* DP0 Audio Current M Value Register */
@@ -277,7 +277,7 @@
 #define AUDIFDATA5             0x071c  /* DP0 Audio Info Frame Bytes 23 to 20 */
 #define AUDIFDATA6             0x0720  /* DP0 Audio Info Frame Bytes 27 to 24 */
 
-#define DP1_SRCCTRL            0x07a0
+#define DP1_SRCCTRL            0x07a0  /* DP1 Control Register */
 
 /* PHY */
 #define DP_PHY_CTRL            0x0800