switch (acp_data->pci_rev) {
case ACP70_PCI_ID:
case ACP71_PCI_ID:
+ case ACP72_PCI_ID:
acp_dma_desc_base_addr = ACP70_DMA_DESC_BASE_ADDR;
acp_dma_desc_max_num_dscr = ACP70_DMA_DESC_MAX_NUM_DSCR;
break;
switch (acp_data->pci_rev) {
case ACP70_PCI_ID:
case ACP71_PCI_ID:
+ case ACP72_PCI_ID:
acp_dma_cntl_0 = ACP70_DMA_CNTL_0;
acp_dma_ch_rst_sts = ACP70_DMA_CH_RST_STS;
acp_dma_dscr_err_sts_0 = ACP70_DMA_ERR_STS_0;
switch (adata->pci_rev) {
case ACP70_PCI_ID:
case ACP71_PCI_ID:
+ case ACP72_PCI_ID:
acp_dma_ch_sts = ACP70_DMA_CH_STS;
break;
default:
switch (adata->pci_rev) {
case ACP70_PCI_ID:
case ACP71_PCI_ID:
+ case ACP72_PCI_ID:
wake_irq_flag = amd_sof_check_and_handle_acp70_sdw_wake_irq(sdev);
break;
}
break;
case ACP70_PCI_ID:
case ACP71_PCI_ID:
+ case ACP72_PCI_ID:
acp_pgfsm_status_mask = ACP70_PGFSM_STATUS_MASK;
acp_pgfsm_cntl_mask = ACP70_PGFSM_CNTL_POWER_ON_MASK;
break;
switch (acp_data->pci_rev) {
case ACP70_PCI_ID:
case ACP71_PCI_ID:
+ case ACP72_PCI_ID:
sdw0_wake_en = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP70_SW0_WAKE_EN);
sdw1_wake_en = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP70_SW1_WAKE_EN);
if (sdw0_wake_en || sdw1_wake_en)
switch (acp_data->pci_rev) {
case ACP70_PCI_ID:
case ACP71_PCI_ID:
+ case ACP72_PCI_ID:
enable = true;
break;
}
switch (acp_data->pci_rev) {
case ACP70_PCI_ID:
case ACP71_PCI_ID:
+ case ACP72_PCI_ID:
snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP70_PME_EN, 1);
break;
}
#define ACP63_PCI_ID 0x63
#define ACP70_PCI_ID 0x70
#define ACP71_PCI_ID 0x71
+#define ACP72_PCI_ID 0x72
#define HOST_BRIDGE_CZN 0x1630
#define HOST_BRIDGE_VGH 0x1645