usb: dwc3: core: set force_gen1 bit in USB31 devices if max speed is SS

Currently for dwc3_usb31 controller, if maximum_speed is limited to
super-speed in DT, then device mode is limited to SS, but host mode
still works in SSP.

The documentation for max-speed property is as follows:

"Tells USB controllers we want to work up to a certain speed.
Incase  this isn't passed via DT, USB controllers should default to
their maximum HW capability."

It doesn't specify that the property is only for device mode.
There are cases where we need to limit the host's maximum speed to
SuperSpeed only. Use this property for host mode to contrain host's
speed to SuperSpeed.

Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
Link: https://lore.kernel.org/r/20231219041559.15789-1-quic_kriskura@quicinc.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index f50b5575d588a44af0903818d58bd5f73a181b64..4447ef2cbc0f01ade237ce8aed9b6a97eef44fb6 100644 (file)
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -1330,6 +1330,18 @@ static int dwc3_core_init(struct dwc3 *dwc)
 
        dwc3_config_threshold(dwc);
 
+       /*
+        * Modify this for all supported Super Speed ports when
+        * multiport support is added.
+        */
+       if (hw_mode != DWC3_GHWPARAMS0_MODE_GADGET &&
+           (DWC3_IP_IS(DWC31)) &&
+           dwc->maximum_speed == USB_SPEED_SUPER) {
+               reg = dwc3_readl(dwc->regs, DWC3_LLUCTL);
+               reg |= DWC3_LLUCTL_FORCE_GEN1;
+               dwc3_writel(dwc->regs, DWC3_LLUCTL, reg);
+       }
+
        return 0;
 
 err_power_off_phy:

diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index efe6caf4d0e873ef030ef55bf0ecbec52b8c91e0..e120611a5174f7589ac124641a7b279654babff6 100644 (file)
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -172,6 +172,8 @@
 #define DWC3_OEVTEN            0xcc0C
 #define DWC3_OSTS              0xcc10
 
+#define DWC3_LLUCTL            0xd024
+
 /* Bit fields */
 
 /* Global SoC Bus Configuration INCRx Register 0 */
@@ -657,6 +659,9 @@
 #define DWC3_OSTS_VBUSVLD              BIT(1)
 #define DWC3_OSTS_CONIDSTS             BIT(0)
 
+/* Force Gen1 speed on Gen2 link */
+#define DWC3_LLUCTL_FORCE_GEN1         BIT(10)
+
 /* Structures */
 
 struct dwc3_trb;