drm/i915/mtl: Add Wa_22015279794

Wa_22015279794 applies to MTL P from stepping A0 to B0 (exclusive).

Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230329212336.106161-3-gustavo.sousa@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 014577971992b103ac1a4768f3c6e9ed2f57dfbc..39593467e1a5dd0abf578d0b6007f05278783238 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1158,7 +1158,13 @@
 #define   ENABLE_EU_COUNT_FOR_TDL_FLUSH                REG_BIT(10)
 #define   DISABLE_ECC                          REG_BIT(5)
 #define   FLOAT_BLEND_OPTIMIZATION_ENABLE      REG_BIT(4)
+/*
+ * We have both ENABLE and DISABLE defines below using the same bit because the
+ * meaning depends on the target platform. There are no platform prefix for them
+ * because different steppings of DG2 pick one or the other semantics.
+ */
 #define   ENABLE_PREFETCH_INTO_IC              REG_BIT(3)
+#define   DISABLE_PREFETCH_INTO_IC             REG_BIT(3)
 
 #define EU_PERF_CNTL0                          PERF_REG(0xe458)
 #define EU_PERF_CNTL4                          PERF_REG(0xe45c)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index f22a43d98925d9609f18ee8bc0b25c38b4724f94..642e57e6e3b47bf1bfc8533b0f06f886c68c4641 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -3060,6 +3060,11 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
                wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
                                 MTL_DISABLE_SAMPLER_SC_OOO);
 
+       if (IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+               /* Wa_22015279794 */
+               wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
+                                DISABLE_PREFETCH_INTO_IC);
+
        if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
            IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
            IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||