drm/amd/display: add dp dto programming function to dccg
authorDillon Varone <dillon.varone@amd.com>
Thu, 24 Aug 2023 16:19:21 +0000 (12:19 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 11 Sep 2023 21:17:17 +0000 (17:17 -0400)
[WHY&HOW]
Add support for programming dp dto via dccg.

Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

index ed8936405dfa5f324e991f5b5f3d11853c25c9c6..75cf4ab8ae3c8963933d08a9fb0353abf50eef70 100644 (file)
@@ -34,6 +34,7 @@
 
 #include "dce_clock_source.h"
 #include "clk_mgr.h"
+#include "dccg.h"
 
 #include "reg_helper.h"
 
index 3e2f0f64c98cae98b05c32e7a0eac9f2694de32d..65bb7cd053858e46f1834d6a9bf2c3bf2c3c9bac 100644 (file)
@@ -56,6 +56,13 @@ enum dentist_dispclk_change_mode {
        DISPCLK_CHANGE_MODE_RAMPING,
 };
 
+struct dp_dto_params {
+       int otg_inst;
+       enum signal_type signal;
+       long long pixclk_hz;
+       long long refclk_hz;
+};
+
 enum pixel_rate_div {
    PIXEL_RATE_DIV_BY_1 = 0,
    PIXEL_RATE_DIV_BY_2 = 1,
@@ -182,6 +189,9 @@ struct dccg_funcs {
                        struct dccg *dccg,
                        uint32_t stream_enc_inst,
                        uint32_t link_enc_inst);
+       void (*set_dp_dto)(
+                       struct dccg *dccg,
+                       const struct dp_dto_params *params);
 };
 
 #endif //__DAL_DCCG_H__