net: aquantia: Prepend hw access functions declarations with prefix
authorIgor Russkikh <igor.russkikh@aquantia.com>
Mon, 15 Jan 2018 13:41:21 +0000 (16:41 +0300)
committerDavid S. Miller <davem@davemloft.net>
Tue, 16 Jan 2018 19:40:01 +0000 (14:40 -0500)
Internal functions for registers and HW access were not prefixed.
This introduce noise in global kernel symbols. Here we add explicit prefix
'hw_atl' to all the HW access layer functions.
Alignment and styling were fixed as well.

Signed-off-by: Igor Russkikh <igor.russkikh@aquantia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c
drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c
drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c
drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.h
drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c

index 5074988bdd489315058715d8f2366b8719197955..4a1c1b96b8b69559d0150302729abab345c6e431 100644 (file)
@@ -62,24 +62,24 @@ static int hw_atl_a0_hw_reset(struct aq_hw_s *self)
 {
        int err = 0;
 
-       glb_glb_reg_res_dis_set(self, 1U);
-       pci_pci_reg_res_dis_set(self, 0U);
-       rx_rx_reg_res_dis_set(self, 0U);
-       tx_tx_reg_res_dis_set(self, 0U);
+       hw_atl_glb_glb_reg_res_dis_set(self, 1U);
+       hw_atl_pci_pci_reg_res_dis_set(self, 0U);
+       hw_atl_rx_rx_reg_res_dis_set(self, 0U);
+       hw_atl_tx_tx_reg_res_dis_set(self, 0U);
 
        HW_ATL_FLUSH();
-       glb_soft_res_set(self, 1);
+       hw_atl_glb_soft_res_set(self, 1);
 
        /* check 10 times by 1ms */
-       AQ_HW_WAIT_FOR(glb_soft_res_get(self) == 0, 1000U, 10U);
+       AQ_HW_WAIT_FOR(hw_atl_glb_soft_res_get(self) == 0, 1000U, 10U);
        if (err < 0)
                goto err_exit;
 
-       itr_irq_reg_res_dis_set(self, 0U);
-       itr_res_irq_set(self, 1U);
+       hw_atl_itr_irq_reg_res_dis_set(self, 0U);
+       hw_atl_itr_res_irq_set(self, 1U);
 
        /* check 10 times by 1ms */
-       AQ_HW_WAIT_FOR(itr_res_irq_get(self) == 0, 1000U, 10U);
+       AQ_HW_WAIT_FOR(hw_atl_itr_res_irq_get(self) == 0, 1000U, 10U);
        if (err < 0)
                goto err_exit;
 
@@ -99,51 +99,53 @@ static int hw_atl_a0_hw_qos_set(struct aq_hw_s *self)
        bool is_rx_flow_control = false;
 
        /* TPS Descriptor rate init */
-       tps_tx_pkt_shed_desc_rate_curr_time_res_set(self, 0x0U);
-       tps_tx_pkt_shed_desc_rate_lim_set(self, 0xA);
+       hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(self, 0x0U);
+       hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(self, 0xA);
 
        /* TPS VM init */
-       tps_tx_pkt_shed_desc_vm_arb_mode_set(self, 0U);
+       hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(self, 0U);
 
        /* TPS TC credits init */
-       tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U);
-       tps_tx_pkt_shed_data_arb_mode_set(self, 0U);
+       hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U);
+       hw_atl_tps_tx_pkt_shed_data_arb_mode_set(self, 0U);
 
-       tps_tx_pkt_shed_tc_data_max_credit_set(self, 0xFFF, 0U);
-       tps_tx_pkt_shed_tc_data_weight_set(self, 0x64, 0U);
-       tps_tx_pkt_shed_desc_tc_max_credit_set(self, 0x50, 0U);
-       tps_tx_pkt_shed_desc_tc_weight_set(self, 0x1E, 0U);
+       hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(self, 0xFFF, 0U);
+       hw_atl_tps_tx_pkt_shed_tc_data_weight_set(self, 0x64, 0U);
+       hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(self, 0x50, 0U);
+       hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(self, 0x1E, 0U);
 
        /* Tx buf size */
        buff_size = HW_ATL_A0_TXBUF_MAX;
 
-       tpb_tx_pkt_buff_size_per_tc_set(self, buff_size, tc);
-       tpb_tx_buff_hi_threshold_per_tc_set(self,
-                                           (buff_size * (1024 / 32U) * 66U) /
-                                           100U, tc);
-       tpb_tx_buff_lo_threshold_per_tc_set(self,
-                                           (buff_size * (1024 / 32U) * 50U) /
-                                           100U, tc);
+       hw_atl_tpb_tx_pkt_buff_size_per_tc_set(self, buff_size, tc);
+       hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(self,
+                                                  (buff_size *
+                                                  (1024 / 32U) * 66U) /
+                                                  100U, tc);
+       hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(self,
+                                                  (buff_size *
+                                                  (1024 / 32U) * 50U) /
+                                                  100U, tc);
 
        /* QoS Rx buf size per TC */
        tc = 0;
        is_rx_flow_control = (AQ_NIC_FC_RX & self->aq_nic_cfg->flow_control);
        buff_size = HW_ATL_A0_RXBUF_MAX;
 
-       rpb_rx_pkt_buff_size_per_tc_set(self, buff_size, tc);
-       rpb_rx_buff_hi_threshold_per_tc_set(self,
-                                           (buff_size *
-                                           (1024U / 32U) * 66U) /
-                                           100U, tc);
-       rpb_rx_buff_lo_threshold_per_tc_set(self,
-                                           (buff_size *
-                                           (1024U / 32U) * 50U) /
-                                           100U, tc);
-       rpb_rx_xoff_en_per_tc_set(self, is_rx_flow_control ? 1U : 0U, tc);
+       hw_atl_rpb_rx_pkt_buff_size_per_tc_set(self, buff_size, tc);
+       hw_atl_rpb_rx_buff_hi_threshold_per_tc_set(self,
+                                                  (buff_size *
+                                                  (1024U / 32U) * 66U) /
+                                                  100U, tc);
+       hw_atl_rpb_rx_buff_lo_threshold_per_tc_set(self,
+                                                  (buff_size *
+                                                  (1024U / 32U) * 50U) /
+                                                  100U, tc);
+       hw_atl_rpb_rx_xoff_en_per_tc_set(self, is_rx_flow_control ? 1U : 0U, tc);
 
        /* QoS 802.1p priority -> TC mapping */
        for (i_priority = 8U; i_priority--;)
-               rpf_rpb_user_priority_tc_map_set(self, i_priority, 0U);
+               hw_atl_rpf_rpb_user_priority_tc_map_set(self, i_priority, 0U);
 
        return aq_hw_err_from_flags(self);
 }
@@ -159,10 +161,11 @@ static int hw_atl_a0_hw_rss_hash_set(struct aq_hw_s *self,
        for (i = 10, addr = 0U; i--; ++addr) {
                u32 key_data = cfg->is_rss ?
                        __swab32(rss_params->hash_secret_key[i]) : 0U;
-               rpf_rss_key_wr_data_set(self, key_data);
-               rpf_rss_key_addr_set(self, addr);
-               rpf_rss_key_wr_en_set(self, 1U);
-               AQ_HW_WAIT_FOR(rpf_rss_key_wr_en_get(self) == 0, 1000U, 10U);
+               hw_atl_rpf_rss_key_wr_data_set(self, key_data);
+               hw_atl_rpf_rss_key_addr_set(self, addr);
+               hw_atl_rpf_rss_key_wr_en_set(self, 1U);
+               AQ_HW_WAIT_FOR(hw_atl_rpf_rss_key_wr_en_get(self) == 0,
+                              1000U, 10U);
                if (err < 0)
                        goto err_exit;
        }
@@ -192,10 +195,11 @@ static int hw_atl_a0_hw_rss_set(struct aq_hw_s *self,
        }
 
        for (i = ARRAY_SIZE(bitary); i--;) {
-               rpf_rss_redir_tbl_wr_data_set(self, bitary[i]);
-               rpf_rss_redir_tbl_addr_set(self, i);
-               rpf_rss_redir_wr_en_set(self, 1U);
-               AQ_HW_WAIT_FOR(rpf_rss_redir_wr_en_get(self) == 0, 1000U, 10U);
+               hw_atl_rpf_rss_redir_tbl_wr_data_set(self, bitary[i]);
+               hw_atl_rpf_rss_redir_tbl_addr_set(self, i);
+               hw_atl_rpf_rss_redir_wr_en_set(self, 1U);
+               AQ_HW_WAIT_FOR(hw_atl_rpf_rss_redir_wr_en_get(self) == 0,
+                              1000U, 10U);
                if (err < 0)
                        goto err_exit;
        }
@@ -210,35 +214,35 @@ static int hw_atl_a0_hw_offload_set(struct aq_hw_s *self,
                                    struct aq_nic_cfg_s *aq_nic_cfg)
 {
        /* TX checksums offloads*/
-       tpo_ipv4header_crc_offload_en_set(self, 1);
-       tpo_tcp_udp_crc_offload_en_set(self, 1);
+       hw_atl_tpo_ipv4header_crc_offload_en_set(self, 1);
+       hw_atl_tpo_tcp_udp_crc_offload_en_set(self, 1);
 
        /* RX checksums offloads*/
-       rpo_ipv4header_crc_offload_en_set(self, 1);
-       rpo_tcp_udp_crc_offload_en_set(self, 1);
+       hw_atl_rpo_ipv4header_crc_offload_en_set(self, 1);
+       hw_atl_rpo_tcp_udp_crc_offload_en_set(self, 1);
 
        /* LSO offloads*/
-       tdm_large_send_offload_en_set(self, 0xFFFFFFFFU);
+       hw_atl_tdm_large_send_offload_en_set(self, 0xFFFFFFFFU);
 
        return aq_hw_err_from_flags(self);
 }
 
 static int hw_atl_a0_hw_init_tx_path(struct aq_hw_s *self)
 {
-       thm_lso_tcp_flag_of_first_pkt_set(self, 0x0FF6U);
-       thm_lso_tcp_flag_of_middle_pkt_set(self, 0x0FF6U);
-       thm_lso_tcp_flag_of_last_pkt_set(self, 0x0F7FU);
+       hw_atl_thm_lso_tcp_flag_of_first_pkt_set(self, 0x0FF6U);
+       hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(self, 0x0FF6U);
+       hw_atl_thm_lso_tcp_flag_of_last_pkt_set(self, 0x0F7FU);
 
        /* Tx interrupts */
-       tdm_tx_desc_wr_wb_irq_en_set(self, 1U);
+       hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 1U);
 
        /* misc */
        aq_hw_write_reg(self, 0x00007040U, IS_CHIP_FEATURE(TPO2) ?
                        0x00010000U : 0x00000000U);
-       tdm_tx_dca_en_set(self, 0U);
-       tdm_tx_dca_mode_set(self, 0U);
+       hw_atl_tdm_tx_dca_en_set(self, 0U);
+       hw_atl_tdm_tx_dca_mode_set(self, 0U);
 
-       tpb_tx_path_scp_ins_en_set(self, 1U);
+       hw_atl_tpb_tx_path_scp_ins_en_set(self, 1U);
 
        return aq_hw_err_from_flags(self);
 }
@@ -249,38 +253,38 @@ static int hw_atl_a0_hw_init_rx_path(struct aq_hw_s *self)
        int i;
 
        /* Rx TC/RSS number config */
-       rpb_rpf_rx_traf_class_mode_set(self, 1U);
+       hw_atl_rpb_rpf_rx_traf_class_mode_set(self, 1U);
 
        /* Rx flow control */
-       rpb_rx_flow_ctl_mode_set(self, 1U);
+       hw_atl_rpb_rx_flow_ctl_mode_set(self, 1U);
 
        /* RSS Ring selection */
-       reg_rx_flr_rss_control1set(self, cfg->is_rss ?
+       hw_atl_reg_rx_flr_rss_control1set(self, cfg->is_rss ?
                                        0xB3333333U : 0x00000000U);
 
        /* Multicast filters */
        for (i = HW_ATL_A0_MAC_MAX; i--;) {
-               rpfl2_uc_flr_en_set(self, (i == 0U) ? 1U : 0U, i);
-               rpfl2unicast_flr_act_set(self, 1U, i);
+               hw_atl_rpfl2_uc_flr_en_set(self, (i == 0U) ? 1U : 0U, i);
+               hw_atl_rpfl2unicast_flr_act_set(self, 1U, i);
        }
 
-       reg_rx_flr_mcst_flr_msk_set(self, 0x00000000U);
-       reg_rx_flr_mcst_flr_set(self, 0x00010FFFU, 0U);
+       hw_atl_reg_rx_flr_mcst_flr_msk_set(self, 0x00000000U);
+       hw_atl_reg_rx_flr_mcst_flr_set(self, 0x00010FFFU, 0U);
 
        /* Vlan filters */
-       rpf_vlan_outer_etht_set(self, 0x88A8U);
-       rpf_vlan_inner_etht_set(self, 0x8100U);
-       rpf_vlan_prom_mode_en_set(self, 1);
+       hw_atl_rpf_vlan_outer_etht_set(self, 0x88A8U);
+       hw_atl_rpf_vlan_inner_etht_set(self, 0x8100U);
+       hw_atl_rpf_vlan_prom_mode_en_set(self, 1);
 
        /* Rx Interrupts */
-       rdm_rx_desc_wr_wb_irq_en_set(self, 1U);
+       hw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 1U);
 
        /* misc */
-       rpfl2broadcast_flr_act_set(self, 1U);
-       rpfl2broadcast_count_threshold_set(self, 0xFFFFU & (~0U / 256U));
+       hw_atl_rpfl2broadcast_flr_act_set(self, 1U);
+       hw_atl_rpfl2broadcast_count_threshold_set(self, 0xFFFFU & (~0U / 256U));
 
-       rdm_rx_dca_en_set(self, 0U);
-       rdm_rx_dca_mode_set(self, 0U);
+       hw_atl_rdm_rx_dca_en_set(self, 0U);
+       hw_atl_rdm_rx_dca_mode_set(self, 0U);
 
        return aq_hw_err_from_flags(self);
 }
@@ -299,10 +303,10 @@ static int hw_atl_a0_hw_mac_addr_set(struct aq_hw_s *self, u8 *mac_addr)
        l = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
                (mac_addr[4] << 8) | mac_addr[5];
 
-       rpfl2_uc_flr_en_set(self, 0U, HW_ATL_A0_MAC);
-       rpfl2unicast_dest_addresslsw_set(self, l, HW_ATL_A0_MAC);
-       rpfl2unicast_dest_addressmsw_set(self, h, HW_ATL_A0_MAC);
-       rpfl2_uc_flr_en_set(self, 1U, HW_ATL_A0_MAC);
+       hw_atl_rpfl2_uc_flr_en_set(self, 0U, HW_ATL_A0_MAC);
+       hw_atl_rpfl2unicast_dest_addresslsw_set(self, l, HW_ATL_A0_MAC);
+       hw_atl_rpfl2unicast_dest_addressmsw_set(self, h, HW_ATL_A0_MAC);
+       hw_atl_rpfl2_uc_flr_en_set(self, 1U, HW_ATL_A0_MAC);
 
        err = aq_hw_err_from_flags(self);
 
@@ -330,8 +334,8 @@ static int hw_atl_a0_hw_init(struct aq_hw_s *self, u8 *mac_addr)
 
        hw_atl_utils_mpi_set(self, MPI_INIT, aq_nic_cfg->link_speed_msk);
 
-       reg_tx_dma_debug_ctl_set(self, 0x800000b8U);
-       reg_tx_dma_debug_ctl_set(self, 0x000000b8U);
+       hw_atl_reg_tx_dma_debug_ctl_set(self, 0x800000b8U);
+       hw_atl_reg_tx_dma_debug_ctl_set(self, 0x000000b8U);
 
        hw_atl_a0_hw_qos_set(self);
        hw_atl_a0_hw_rss_set(self, &aq_nic_cfg->aq_rss);
@@ -346,19 +350,18 @@ static int hw_atl_a0_hw_init(struct aq_hw_s *self, u8 *mac_addr)
                goto err_exit;
 
        /* Interrupts */
-       reg_irq_glb_ctl_set(self,
-                           aq_hw_atl_igcr_table_[aq_nic_cfg->irq_type]
-                                                [(aq_nic_cfg->vecs > 1U) ?
-                                                1 : 0]);
+       hw_atl_reg_irq_glb_ctl_set(self,
+                                  aq_hw_atl_igcr_table_[aq_nic_cfg->irq_type]
+                                       [(aq_nic_cfg->vecs > 1U) ? 1 : 0]);
 
-       itr_irq_auto_masklsw_set(self, aq_nic_cfg->aq_hw_caps->irq_mask);
+       hw_atl_itr_irq_auto_masklsw_set(self, aq_nic_cfg->aq_hw_caps->irq_mask);
 
        /* Interrupts */
-       reg_gen_irq_map_set(self,
-                           ((HW_ATL_A0_ERR_INT << 0x18) | (1U << 0x1F)) |
-                           ((HW_ATL_A0_ERR_INT << 0x10) | (1U << 0x17)) |
-                           ((HW_ATL_A0_ERR_INT << 8) | (1U << 0xF)) |
-                           ((HW_ATL_A0_ERR_INT) | (1U << 0x7)), 0U);
+       hw_atl_reg_gen_irq_map_set(self,
+                                  ((HW_ATL_A0_ERR_INT << 0x18) | (1U << 0x1F)) |
+                                  ((HW_ATL_A0_ERR_INT << 0x10) | (1U << 0x17)) |
+                                  ((HW_ATL_A0_ERR_INT << 8) | (1U << 0xF)) |
+                                  ((HW_ATL_A0_ERR_INT) | (1U << 0x7)), 0U);
 
        hw_atl_a0_hw_offload_set(self, aq_nic_cfg);
 
@@ -369,28 +372,28 @@ err_exit:
 static int hw_atl_a0_hw_ring_tx_start(struct aq_hw_s *self,
                                      struct aq_ring_s *ring)
 {
-       tdm_tx_desc_en_set(self, 1, ring->idx);
+       hw_atl_tdm_tx_desc_en_set(self, 1, ring->idx);
        return aq_hw_err_from_flags(self);
 }
 
 static int hw_atl_a0_hw_ring_rx_start(struct aq_hw_s *self,
                                      struct aq_ring_s *ring)
 {
-       rdm_rx_desc_en_set(self, 1, ring->idx);
+       hw_atl_rdm_rx_desc_en_set(self, 1, ring->idx);
        return aq_hw_err_from_flags(self);
 }
 
 static int hw_atl_a0_hw_start(struct aq_hw_s *self)
 {
-       tpb_tx_buff_en_set(self, 1);
-       rpb_rx_buff_en_set(self, 1);
+       hw_atl_tpb_tx_buff_en_set(self, 1);
+       hw_atl_rpb_rx_buff_en_set(self, 1);
        return aq_hw_err_from_flags(self);
 }
 
 static int hw_atl_a0_hw_tx_ring_tail_update(struct aq_hw_s *self,
                                            struct aq_ring_s *ring)
 {
-       reg_tx_dma_desc_tail_ptr_set(self, ring->sw_tail, ring->idx);
+       hw_atl_reg_tx_dma_desc_tail_ptr_set(self, ring->sw_tail, ring->idx);
        return 0;
 }
 
@@ -476,36 +479,37 @@ static int hw_atl_a0_hw_ring_rx_init(struct aq_hw_s *self,
        u32 dma_desc_addr_lsw = (u32)aq_ring->dx_ring_pa;
        u32 dma_desc_addr_msw = (u32)(((u64)aq_ring->dx_ring_pa) >> 32);
 
-       rdm_rx_desc_en_set(self, false, aq_ring->idx);
+       hw_atl_rdm_rx_desc_en_set(self, false, aq_ring->idx);
 
-       rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx);
+       hw_atl_rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx);
 
-       reg_rx_dma_desc_base_addresslswset(self, dma_desc_addr_lsw,
-                                          aq_ring->idx);
+       hw_atl_reg_rx_dma_desc_base_addresslswset(self, dma_desc_addr_lsw,
+                                                 aq_ring->idx);
 
-       reg_rx_dma_desc_base_addressmswset(self,
-                                          dma_desc_addr_msw, aq_ring->idx);
+       hw_atl_reg_rx_dma_desc_base_addressmswset(self,
+                                                 dma_desc_addr_msw,
+                                                 aq_ring->idx);
 
-       rdm_rx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx);
+       hw_atl_rdm_rx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx);
 
-       rdm_rx_desc_data_buff_size_set(self,
-                                      AQ_CFG_RX_FRAME_MAX / 1024U,
+       hw_atl_rdm_rx_desc_data_buff_size_set(self,
+                                             AQ_CFG_RX_FRAME_MAX / 1024U,
                                       aq_ring->idx);
 
-       rdm_rx_desc_head_buff_size_set(self, 0U, aq_ring->idx);
-       rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx);
-       rpo_rx_desc_vlan_stripping_set(self, 0U, aq_ring->idx);
+       hw_atl_rdm_rx_desc_head_buff_size_set(self, 0U, aq_ring->idx);
+       hw_atl_rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx);
+       hw_atl_rpo_rx_desc_vlan_stripping_set(self, 0U, aq_ring->idx);
 
        /* Rx ring set mode */
 
        /* Mapping interrupt vector */
-       itr_irq_map_rx_set(self, aq_ring_param->vec_idx, aq_ring->idx);
-       itr_irq_map_en_rx_set(self, true, aq_ring->idx);
+       hw_atl_itr_irq_map_rx_set(self, aq_ring_param->vec_idx, aq_ring->idx);
+       hw_atl_itr_irq_map_en_rx_set(self, true, aq_ring->idx);
 
-       rdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx);
-       rdm_rx_desc_dca_en_set(self, 0U, aq_ring->idx);
-       rdm_rx_head_dca_en_set(self, 0U, aq_ring->idx);
-       rdm_rx_pld_dca_en_set(self, 0U, aq_ring->idx);
+       hw_atl_rdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx);
+       hw_atl_rdm_rx_desc_dca_en_set(self, 0U, aq_ring->idx);
+       hw_atl_rdm_rx_head_dca_en_set(self, 0U, aq_ring->idx);
+       hw_atl_rdm_rx_pld_dca_en_set(self, 0U, aq_ring->idx);
 
        return aq_hw_err_from_flags(self);
 }
@@ -517,25 +521,25 @@ static int hw_atl_a0_hw_ring_tx_init(struct aq_hw_s *self,
        u32 dma_desc_lsw_addr = (u32)aq_ring->dx_ring_pa;
        u32 dma_desc_msw_addr = (u32)(((u64)aq_ring->dx_ring_pa) >> 32);
 
-       reg_tx_dma_desc_base_addresslswset(self, dma_desc_lsw_addr,
-                                          aq_ring->idx);
+       hw_atl_reg_tx_dma_desc_base_addresslswset(self, dma_desc_lsw_addr,
+                                                 aq_ring->idx);
 
-       reg_tx_dma_desc_base_addressmswset(self, dma_desc_msw_addr,
-                                          aq_ring->idx);
+       hw_atl_reg_tx_dma_desc_base_addressmswset(self, dma_desc_msw_addr,
+                                                 aq_ring->idx);
 
-       tdm_tx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx);
+       hw_atl_tdm_tx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx);
 
        hw_atl_a0_hw_tx_ring_tail_update(self, aq_ring);
 
        /* Set Tx threshold */
-       tdm_tx_desc_wr_wb_threshold_set(self, 0U, aq_ring->idx);
+       hw_atl_tdm_tx_desc_wr_wb_threshold_set(self, 0U, aq_ring->idx);
 
        /* Mapping interrupt vector */
-       itr_irq_map_tx_set(self, aq_ring_param->vec_idx, aq_ring->idx);
-       itr_irq_map_en_tx_set(self, true, aq_ring->idx);
+       hw_atl_itr_irq_map_tx_set(self, aq_ring_param->vec_idx, aq_ring->idx);
+       hw_atl_itr_irq_map_en_tx_set(self, true, aq_ring->idx);
 
-       tdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx);
-       tdm_tx_desc_dca_en_set(self, 0U, aq_ring->idx);
+       hw_atl_tdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx);
+       hw_atl_tdm_tx_desc_dca_en_set(self, 0U, aq_ring->idx);
 
        return aq_hw_err_from_flags(self);
 }
@@ -556,7 +560,7 @@ static int hw_atl_a0_hw_ring_rx_fill(struct aq_hw_s *self,
                rxd->hdr_addr = 0U;
        }
 
-       reg_rx_dma_desc_tail_ptr_set(self, sw_tail_old, ring->idx);
+       hw_atl_reg_rx_dma_desc_tail_ptr_set(self, sw_tail_old, ring->idx);
 
        return aq_hw_err_from_flags(self);
 }
@@ -565,13 +569,13 @@ static int hw_atl_a0_hw_ring_tx_head_update(struct aq_hw_s *self,
                                            struct aq_ring_s *ring)
 {
        int err = 0;
-       unsigned int hw_head_ = tdm_tx_desc_head_ptr_get(self, ring->idx);
+       unsigned int hw_head = hw_atl_tdm_tx_desc_head_ptr_get(self, ring->idx);
 
        if (aq_utils_obj_test(&self->flags, AQ_HW_FLAG_ERR_UNPLUG)) {
                err = -ENXIO;
                goto err_exit;
        }
-       ring->hw_head = hw_head_;
+       ring->hw_head = hw_head;
        err = aq_hw_err_from_flags(self);
 
 err_exit:
@@ -595,15 +599,16 @@ static int hw_atl_a0_hw_ring_rx_receive(struct aq_hw_s *self,
 
                if (!(rxd_wb->status & 0x5U)) { /* RxD is not done */
                        if ((1U << 4) &
-                               reg_rx_dma_desc_status_get(self, ring->idx)) {
-                       rdm_rx_desc_en_set(self, false, ring->idx);
-                       rdm_rx_desc_res_set(self, true, ring->idx);
-                       rdm_rx_desc_res_set(self, false, ring->idx);
-                       rdm_rx_desc_en_set(self, true, ring->idx);
+                       hw_atl_reg_rx_dma_desc_status_get(self, ring->idx)) {
+                               hw_atl_rdm_rx_desc_en_set(self, false, ring->idx);
+                               hw_atl_rdm_rx_desc_res_set(self, true, ring->idx);
+                               hw_atl_rdm_rx_desc_res_set(self, false, ring->idx);
+                               hw_atl_rdm_rx_desc_en_set(self, true, ring->idx);
                        }
 
                        if (ring->hw_head ||
-                           (rdm_rx_desc_head_ptr_get(self, ring->idx) < 2U)) {
+                           (hw_atl_rdm_rx_desc_head_ptr_get(self,
+                                                            ring->idx) < 2U)) {
                                break;
                        } else if (!(rxd_wb->status & 0x1U)) {
                                struct hw_atl_rxd_wb_s *rxd_wb1 =
@@ -686,17 +691,17 @@ static int hw_atl_a0_hw_ring_rx_receive(struct aq_hw_s *self,
 
 static int hw_atl_a0_hw_irq_enable(struct aq_hw_s *self, u64 mask)
 {
-       itr_irq_msk_setlsw_set(self, LODWORD(mask) |
+       hw_atl_itr_irq_msk_setlsw_set(self, LODWORD(mask) |
                               (1U << HW_ATL_A0_ERR_INT));
        return aq_hw_err_from_flags(self);
 }
 
 static int hw_atl_a0_hw_irq_disable(struct aq_hw_s *self, u64 mask)
 {
-       itr_irq_msk_clearlsw_set(self, LODWORD(mask));
-       itr_irq_status_clearlsw_set(self, LODWORD(mask));
+       hw_atl_itr_irq_msk_clearlsw_set(self, LODWORD(mask));
+       hw_atl_itr_irq_status_clearlsw_set(self, LODWORD(mask));
 
-       if ((1U << 16) & reg_gen_irq_status_get(self))
+       if ((1U << 16) & hw_atl_reg_gen_irq_status_get(self))
                atomic_inc(&self->dpc);
 
        return aq_hw_err_from_flags(self);
@@ -704,7 +709,7 @@ static int hw_atl_a0_hw_irq_disable(struct aq_hw_s *self, u64 mask)
 
 static int hw_atl_a0_hw_irq_read(struct aq_hw_s *self, u64 *mask)
 {
-       *mask = itr_irq_statuslsw_get(self);
+       *mask = hw_atl_itr_irq_statuslsw_get(self);
        return aq_hw_err_from_flags(self);
 }
 
@@ -715,18 +720,20 @@ static int hw_atl_a0_hw_packet_filter_set(struct aq_hw_s *self,
 {
        unsigned int i = 0U;
 
-       rpfl2promiscuous_mode_en_set(self, IS_FILTER_ENABLED(IFF_PROMISC));
-       rpfl2multicast_flr_en_set(self, IS_FILTER_ENABLED(IFF_MULTICAST), 0);
-       rpfl2broadcast_en_set(self, IS_FILTER_ENABLED(IFF_BROADCAST));
+       hw_atl_rpfl2promiscuous_mode_en_set(self,
+                                           IS_FILTER_ENABLED(IFF_PROMISC));
+       hw_atl_rpfl2multicast_flr_en_set(self,
+                                        IS_FILTER_ENABLED(IFF_MULTICAST), 0);
+       hw_atl_rpfl2broadcast_en_set(self, IS_FILTER_ENABLED(IFF_BROADCAST));
 
        self->aq_nic_cfg->is_mc_list_enabled =
                        IS_FILTER_ENABLED(IFF_MULTICAST);
 
        for (i = HW_ATL_A0_MAC_MIN; i < HW_ATL_A0_MAC_MAX; ++i)
-               rpfl2_uc_flr_en_set(self,
-                                   (self->aq_nic_cfg->is_mc_list_enabled &&
-                                   (i <= self->aq_nic_cfg->mc_list_count)) ?
-                                   1U : 0U, i);
+               hw_atl_rpfl2_uc_flr_en_set(self,
+                                          (self->aq_nic_cfg->is_mc_list_enabled &&
+                                          (i <= self->aq_nic_cfg->mc_list_count)) ?
+                                           1U : 0U, i);
 
        return aq_hw_err_from_flags(self);
 }
@@ -753,17 +760,19 @@ static int hw_atl_a0_hw_multicast_list_set(struct aq_hw_s *self,
                u32 l = (ar_mac[i][2] << 24) | (ar_mac[i][3] << 16) |
                                        (ar_mac[i][4] << 8) | ar_mac[i][5];
 
-               rpfl2_uc_flr_en_set(self, 0U, HW_ATL_A0_MAC_MIN + i);
+               hw_atl_rpfl2_uc_flr_en_set(self, 0U, HW_ATL_A0_MAC_MIN + i);
 
-               rpfl2unicast_dest_addresslsw_set(self,
-                                                l, HW_ATL_A0_MAC_MIN + i);
+               hw_atl_rpfl2unicast_dest_addresslsw_set(self,
+                                                       l,
+                                                       HW_ATL_A0_MAC_MIN + i);
 
-               rpfl2unicast_dest_addressmsw_set(self,
-                                                h, HW_ATL_A0_MAC_MIN + i);
+               hw_atl_rpfl2unicast_dest_addressmsw_set(self,
+                                                       h,
+                                                       HW_ATL_A0_MAC_MIN + i);
 
-               rpfl2_uc_flr_en_set(self,
-                                   (self->aq_nic_cfg->is_mc_list_enabled),
-                                   HW_ATL_A0_MAC_MIN + i);
+               hw_atl_rpfl2_uc_flr_en_set(self,
+                                          (self->aq_nic_cfg->is_mc_list_enabled),
+                                          HW_ATL_A0_MAC_MIN + i);
        }
 
        err = aq_hw_err_from_flags(self);
@@ -815,7 +824,7 @@ static int hw_atl_a0_hw_interrupt_moderation_set(struct aq_hw_s *self)
        }
 
        for (i = HW_ATL_A0_RINGS_MAX; i--;)
-               reg_irq_thr_set(self, itr_rx, i);
+               hw_atl_reg_irq_thr_set(self, itr_rx, i);
 
        return aq_hw_err_from_flags(self);
 }
@@ -829,14 +838,14 @@ static int hw_atl_a0_hw_stop(struct aq_hw_s *self)
 static int hw_atl_a0_hw_ring_tx_stop(struct aq_hw_s *self,
                                     struct aq_ring_s *ring)
 {
-       tdm_tx_desc_en_set(self, 0U, ring->idx);
+       hw_atl_tdm_tx_desc_en_set(self, 0U, ring->idx);
        return aq_hw_err_from_flags(self);
 }
 
 static int hw_atl_a0_hw_ring_rx_stop(struct aq_hw_s *self,
                                     struct aq_ring_s *ring)
 {
-       rdm_rx_desc_en_set(self, 0U, ring->idx);
+       hw_atl_rdm_rx_desc_en_set(self, 0U, ring->idx);
        return aq_hw_err_from_flags(self);
 }
 
index 79e59b73992f744098d23aec2dea7e00bf688afd..0b090161ed7934710a4bc9f7ae9d99366d58241f 100644 (file)
@@ -63,24 +63,24 @@ static int hw_atl_b0_hw_reset(struct aq_hw_s *self)
 {
        int err = 0;
 
-       glb_glb_reg_res_dis_set(self, 1U);
-       pci_pci_reg_res_dis_set(self, 0U);
-       rx_rx_reg_res_dis_set(self, 0U);
-       tx_tx_reg_res_dis_set(self, 0U);
+       hw_atl_glb_glb_reg_res_dis_set(self, 1U);
+       hw_atl_pci_pci_reg_res_dis_set(self, 0U);
+       hw_atl_rx_rx_reg_res_dis_set(self, 0U);
+       hw_atl_tx_tx_reg_res_dis_set(self, 0U);
 
        HW_ATL_FLUSH();
-       glb_soft_res_set(self, 1);
+       hw_atl_glb_soft_res_set(self, 1);
 
        /* check 10 times by 1ms */
-       AQ_HW_WAIT_FOR(glb_soft_res_get(self) == 0, 1000U, 10U);
+       AQ_HW_WAIT_FOR(hw_atl_glb_soft_res_get(self) == 0, 1000U, 10U);
        if (err < 0)
                goto err_exit;
 
-       itr_irq_reg_res_dis_set(self, 0U);
-       itr_res_irq_set(self, 1U);
+       hw_atl_itr_irq_reg_res_dis_set(self, 0U);
+       hw_atl_itr_res_irq_set(self, 1U);
 
        /* check 10 times by 1ms */
-       AQ_HW_WAIT_FOR(itr_res_irq_get(self) == 0, 1000U, 10U);
+       AQ_HW_WAIT_FOR(hw_atl_itr_res_irq_get(self) == 0, 1000U, 10U);
        if (err < 0)
                goto err_exit;
 
@@ -100,51 +100,53 @@ static int hw_atl_b0_hw_qos_set(struct aq_hw_s *self)
        bool is_rx_flow_control = false;
 
        /* TPS Descriptor rate init */
-       tps_tx_pkt_shed_desc_rate_curr_time_res_set(self, 0x0U);
-       tps_tx_pkt_shed_desc_rate_lim_set(self, 0xA);
+       hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(self, 0x0U);
+       hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(self, 0xA);
 
        /* TPS VM init */
-       tps_tx_pkt_shed_desc_vm_arb_mode_set(self, 0U);
+       hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(self, 0U);
 
        /* TPS TC credits init */
-       tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U);
-       tps_tx_pkt_shed_data_arb_mode_set(self, 0U);
+       hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U);
+       hw_atl_tps_tx_pkt_shed_data_arb_mode_set(self, 0U);
 
-       tps_tx_pkt_shed_tc_data_max_credit_set(self, 0xFFF, 0U);
-       tps_tx_pkt_shed_tc_data_weight_set(self, 0x64, 0U);
-       tps_tx_pkt_shed_desc_tc_max_credit_set(self, 0x50, 0U);
-       tps_tx_pkt_shed_desc_tc_weight_set(self, 0x1E, 0U);
+       hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(self, 0xFFF, 0U);
+       hw_atl_tps_tx_pkt_shed_tc_data_weight_set(self, 0x64, 0U);
+       hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(self, 0x50, 0U);
+       hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(self, 0x1E, 0U);
 
        /* Tx buf size */
        buff_size = HW_ATL_B0_TXBUF_MAX;
 
-       tpb_tx_pkt_buff_size_per_tc_set(self, buff_size, tc);
-       tpb_tx_buff_hi_threshold_per_tc_set(self,
-                                           (buff_size * (1024 / 32U) * 66U) /
-                                           100U, tc);
-       tpb_tx_buff_lo_threshold_per_tc_set(self,
-                                           (buff_size * (1024 / 32U) * 50U) /
-                                           100U, tc);
+       hw_atl_tpb_tx_pkt_buff_size_per_tc_set(self, buff_size, tc);
+       hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(self,
+                                                  (buff_size *
+                                                  (1024 / 32U) * 66U) /
+                                                  100U, tc);
+       hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(self,
+                                                  (buff_size *
+                                                  (1024 / 32U) * 50U) /
+                                                  100U, tc);
 
        /* QoS Rx buf size per TC */
        tc = 0;
        is_rx_flow_control = (AQ_NIC_FC_RX & self->aq_nic_cfg->flow_control);
        buff_size = HW_ATL_B0_RXBUF_MAX;
 
-       rpb_rx_pkt_buff_size_per_tc_set(self, buff_size, tc);
-       rpb_rx_buff_hi_threshold_per_tc_set(self,
-                                           (buff_size *
-                                           (1024U / 32U) * 66U) /
-                                           100U, tc);
-       rpb_rx_buff_lo_threshold_per_tc_set(self,
-                                           (buff_size *
-                                           (1024U / 32U) * 50U) /
-                                           100U, tc);
-       rpb_rx_xoff_en_per_tc_set(self, is_rx_flow_control ? 1U : 0U, tc);
+       hw_atl_rpb_rx_pkt_buff_size_per_tc_set(self, buff_size, tc);
+       hw_atl_rpb_rx_buff_hi_threshold_per_tc_set(self,
+                                                  (buff_size *
+                                                  (1024U / 32U) * 66U) /
+                                                  100U, tc);
+       hw_atl_rpb_rx_buff_lo_threshold_per_tc_set(self,
+                                                  (buff_size *
+                                                  (1024U / 32U) * 50U) /
+                                                  100U, tc);
+       hw_atl_rpb_rx_xoff_en_per_tc_set(self, is_rx_flow_control ? 1U : 0U, tc);
 
        /* QoS 802.1p priority -> TC mapping */
        for (i_priority = 8U; i_priority--;)
-               rpf_rpb_user_priority_tc_map_set(self, i_priority, 0U);
+               hw_atl_rpf_rpb_user_priority_tc_map_set(self, i_priority, 0U);
 
        return aq_hw_err_from_flags(self);
 }
@@ -160,10 +162,11 @@ static int hw_atl_b0_hw_rss_hash_set(struct aq_hw_s *self,
        for (i = 10, addr = 0U; i--; ++addr) {
                u32 key_data = cfg->is_rss ?
                        __swab32(rss_params->hash_secret_key[i]) : 0U;
-               rpf_rss_key_wr_data_set(self, key_data);
-               rpf_rss_key_addr_set(self, addr);
-               rpf_rss_key_wr_en_set(self, 1U);
-               AQ_HW_WAIT_FOR(rpf_rss_key_wr_en_get(self) == 0, 1000U, 10U);
+               hw_atl_rpf_rss_key_wr_data_set(self, key_data);
+               hw_atl_rpf_rss_key_addr_set(self, addr);
+               hw_atl_rpf_rss_key_wr_en_set(self, 1U);
+               AQ_HW_WAIT_FOR(hw_atl_rpf_rss_key_wr_en_get(self) == 0,
+                              1000U, 10U);
                if (err < 0)
                        goto err_exit;
        }
@@ -193,10 +196,11 @@ static int hw_atl_b0_hw_rss_set(struct aq_hw_s *self,
        }
 
        for (i = ARRAY_SIZE(bitary); i--;) {
-               rpf_rss_redir_tbl_wr_data_set(self, bitary[i]);
-               rpf_rss_redir_tbl_addr_set(self, i);
-               rpf_rss_redir_wr_en_set(self, 1U);
-               AQ_HW_WAIT_FOR(rpf_rss_redir_wr_en_get(self) == 0, 1000U, 10U);
+               hw_atl_rpf_rss_redir_tbl_wr_data_set(self, bitary[i]);
+               hw_atl_rpf_rss_redir_tbl_addr_set(self, i);
+               hw_atl_rpf_rss_redir_wr_en_set(self, 1U);
+               AQ_HW_WAIT_FOR(hw_atl_rpf_rss_redir_wr_en_get(self) == 0,
+                              1000U, 10U);
                if (err < 0)
                        goto err_exit;
        }
@@ -213,15 +217,15 @@ static int hw_atl_b0_hw_offload_set(struct aq_hw_s *self,
        unsigned int i;
 
        /* TX checksums offloads*/
-       tpo_ipv4header_crc_offload_en_set(self, 1);
-       tpo_tcp_udp_crc_offload_en_set(self, 1);
+       hw_atl_tpo_ipv4header_crc_offload_en_set(self, 1);
+       hw_atl_tpo_tcp_udp_crc_offload_en_set(self, 1);
 
        /* RX checksums offloads*/
-       rpo_ipv4header_crc_offload_en_set(self, 1);
-       rpo_tcp_udp_crc_offload_en_set(self, 1);
+       hw_atl_rpo_ipv4header_crc_offload_en_set(self, 1);
+       hw_atl_rpo_tcp_udp_crc_offload_en_set(self, 1);
 
        /* LSO offloads*/
-       tdm_large_send_offload_en_set(self, 0xFFFFFFFFU);
+       hw_atl_tdm_large_send_offload_en_set(self, 0xFFFFFFFFU);
 
 /* LRO offloads */
        {
@@ -230,43 +234,44 @@ static int hw_atl_b0_hw_offload_set(struct aq_hw_s *self,
                        ((2U < HW_ATL_B0_LRO_RXD_MAX) ? 0x1U : 0x0));
 
                for (i = 0; i < HW_ATL_B0_RINGS_MAX; i++)
-                       rpo_lro_max_num_of_descriptors_set(self, val, i);
+                       hw_atl_rpo_lro_max_num_of_descriptors_set(self, val, i);
 
-               rpo_lro_time_base_divider_set(self, 0x61AU);
-               rpo_lro_inactive_interval_set(self, 0);
-               rpo_lro_max_coalescing_interval_set(self, 2);
+               hw_atl_rpo_lro_time_base_divider_set(self, 0x61AU);
+               hw_atl_rpo_lro_inactive_interval_set(self, 0);
+               hw_atl_rpo_lro_max_coalescing_interval_set(self, 2);
 
-               rpo_lro_qsessions_lim_set(self, 1U);
+               hw_atl_rpo_lro_qsessions_lim_set(self, 1U);
 
-               rpo_lro_total_desc_lim_set(self, 2U);
+               hw_atl_rpo_lro_total_desc_lim_set(self, 2U);
 
-               rpo_lro_patch_optimization_en_set(self, 0U);
+               hw_atl_rpo_lro_patch_optimization_en_set(self, 0U);
 
-               rpo_lro_min_pay_of_first_pkt_set(self, 10U);
+               hw_atl_rpo_lro_min_pay_of_first_pkt_set(self, 10U);
 
-               rpo_lro_pkt_lim_set(self, 1U);
+               hw_atl_rpo_lro_pkt_lim_set(self, 1U);
 
-               rpo_lro_en_set(self, aq_nic_cfg->is_lro ? 0xFFFFFFFFU : 0U);
+               hw_atl_rpo_lro_en_set(self,
+                                     aq_nic_cfg->is_lro ? 0xFFFFFFFFU : 0U);
        }
        return aq_hw_err_from_flags(self);
 }
 
 static int hw_atl_b0_hw_init_tx_path(struct aq_hw_s *self)
 {
-       thm_lso_tcp_flag_of_first_pkt_set(self, 0x0FF6U);
-       thm_lso_tcp_flag_of_middle_pkt_set(self, 0x0FF6U);
-       thm_lso_tcp_flag_of_last_pkt_set(self, 0x0F7FU);
+       hw_atl_thm_lso_tcp_flag_of_first_pkt_set(self, 0x0FF6U);
+       hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(self, 0x0FF6U);
+       hw_atl_thm_lso_tcp_flag_of_last_pkt_set(self, 0x0F7FU);
 
        /* Tx interrupts */
-       tdm_tx_desc_wr_wb_irq_en_set(self, 1U);
+       hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 1U);
 
        /* misc */
        aq_hw_write_reg(self, 0x00007040U, IS_CHIP_FEATURE(TPO2) ?
                        0x00010000U : 0x00000000U);
-       tdm_tx_dca_en_set(self, 0U);
-       tdm_tx_dca_mode_set(self, 0U);
+       hw_atl_tdm_tx_dca_en_set(self, 0U);
+       hw_atl_tdm_tx_dca_mode_set(self, 0U);
 
-       tpb_tx_path_scp_ins_en_set(self, 1U);
+       hw_atl_tpb_tx_path_scp_ins_en_set(self, 1U);
 
        return aq_hw_err_from_flags(self);
 }
@@ -277,55 +282,55 @@ static int hw_atl_b0_hw_init_rx_path(struct aq_hw_s *self)
        int i;
 
        /* Rx TC/RSS number config */
-       rpb_rpf_rx_traf_class_mode_set(self, 1U);
+       hw_atl_rpb_rpf_rx_traf_class_mode_set(self, 1U);
 
        /* Rx flow control */
-       rpb_rx_flow_ctl_mode_set(self, 1U);
+       hw_atl_rpb_rx_flow_ctl_mode_set(self, 1U);
 
        /* RSS Ring selection */
-       reg_rx_flr_rss_control1set(self, cfg->is_rss ?
+       hw_atl_reg_rx_flr_rss_control1set(self, cfg->is_rss ?
                                        0xB3333333U : 0x00000000U);
 
        /* Multicast filters */
        for (i = HW_ATL_B0_MAC_MAX; i--;) {
-               rpfl2_uc_flr_en_set(self, (i == 0U) ? 1U : 0U, i);
-               rpfl2unicast_flr_act_set(self, 1U, i);
+               hw_atl_rpfl2_uc_flr_en_set(self, (i == 0U) ? 1U : 0U, i);
+               hw_atl_rpfl2unicast_flr_act_set(self, 1U, i);
        }
 
-       reg_rx_flr_mcst_flr_msk_set(self, 0x00000000U);
-       reg_rx_flr_mcst_flr_set(self, 0x00010FFFU, 0U);
+       hw_atl_reg_rx_flr_mcst_flr_msk_set(self, 0x00000000U);
+       hw_atl_reg_rx_flr_mcst_flr_set(self, 0x00010FFFU, 0U);
 
        /* Vlan filters */
-       rpf_vlan_outer_etht_set(self, 0x88A8U);
-       rpf_vlan_inner_etht_set(self, 0x8100U);
+       hw_atl_rpf_vlan_outer_etht_set(self, 0x88A8U);
+       hw_atl_rpf_vlan_inner_etht_set(self, 0x8100U);
 
        if (cfg->vlan_id) {
-               rpf_vlan_flr_act_set(self, 1U, 0U);
-               rpf_vlan_id_flr_set(self, 0U, 0U);
-               rpf_vlan_flr_en_set(self, 0U, 0U);
+               hw_atl_rpf_vlan_flr_act_set(self, 1U, 0U);
+               hw_atl_rpf_vlan_id_flr_set(self, 0U, 0U);
+               hw_atl_rpf_vlan_flr_en_set(self, 0U, 0U);
 
-               rpf_vlan_accept_untagged_packets_set(self, 1U);
-               rpf_vlan_untagged_act_set(self, 1U);
+               hw_atl_rpf_vlan_accept_untagged_packets_set(self, 1U);
+               hw_atl_rpf_vlan_untagged_act_set(self, 1U);
 
-               rpf_vlan_flr_act_set(self, 1U, 1U);
-               rpf_vlan_id_flr_set(self, cfg->vlan_id, 0U);
-               rpf_vlan_flr_en_set(self, 1U, 1U);
+               hw_atl_rpf_vlan_flr_act_set(self, 1U, 1U);
+               hw_atl_rpf_vlan_id_flr_set(self, cfg->vlan_id, 0U);
+               hw_atl_rpf_vlan_flr_en_set(self, 1U, 1U);
        } else {
-               rpf_vlan_prom_mode_en_set(self, 1);
+               hw_atl_rpf_vlan_prom_mode_en_set(self, 1);
        }
 
        /* Rx Interrupts */
-       rdm_rx_desc_wr_wb_irq_en_set(self, 1U);
+       hw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 1U);
 
        /* misc */
        aq_hw_write_reg(self, 0x00005040U,
                        IS_CHIP_FEATURE(RPF2) ? 0x000F0000U : 0x00000000U);
 
-       rpfl2broadcast_flr_act_set(self, 1U);
-       rpfl2broadcast_count_threshold_set(self, 0xFFFFU & (~0U / 256U));
+       hw_atl_rpfl2broadcast_flr_act_set(self, 1U);
+       hw_atl_rpfl2broadcast_count_threshold_set(self, 0xFFFFU & (~0U / 256U));
 
-       rdm_rx_dca_en_set(self, 0U);
-       rdm_rx_dca_mode_set(self, 0U);
+       hw_atl_rdm_rx_dca_en_set(self, 0U);
+       hw_atl_rdm_rx_dca_mode_set(self, 0U);
 
        return aq_hw_err_from_flags(self);
 }
@@ -344,10 +349,10 @@ static int hw_atl_b0_hw_mac_addr_set(struct aq_hw_s *self, u8 *mac_addr)
        l = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
                (mac_addr[4] << 8) | mac_addr[5];
 
-       rpfl2_uc_flr_en_set(self, 0U, HW_ATL_B0_MAC);
-       rpfl2unicast_dest_addresslsw_set(self, l, HW_ATL_B0_MAC);
-       rpfl2unicast_dest_addressmsw_set(self, h, HW_ATL_B0_MAC);
-       rpfl2_uc_flr_en_set(self, 1U, HW_ATL_B0_MAC);
+       hw_atl_rpfl2_uc_flr_en_set(self, 0U, HW_ATL_B0_MAC);
+       hw_atl_rpfl2unicast_dest_addresslsw_set(self, l, HW_ATL_B0_MAC);
+       hw_atl_rpfl2unicast_dest_addressmsw_set(self, h, HW_ATL_B0_MAC);
+       hw_atl_rpfl2_uc_flr_en_set(self, 1U, HW_ATL_B0_MAC);
 
        err = aq_hw_err_from_flags(self);
 
@@ -400,16 +405,16 @@ static int hw_atl_b0_hw_init(struct aq_hw_s *self, u8 *mac_addr)
                goto err_exit;
 
        /* Interrupts */
-       reg_irq_glb_ctl_set(self,
-                           aq_hw_atl_igcr_table_[aq_nic_cfg->irq_type]
+       hw_atl_reg_irq_glb_ctl_set(self,
+                                  aq_hw_atl_igcr_table_[aq_nic_cfg->irq_type]
                                                 [(aq_nic_cfg->vecs > 1U) ?
                                                 1 : 0]);
 
-       itr_irq_auto_masklsw_set(self, aq_nic_cfg->aq_hw_caps->irq_mask);
+       hw_atl_itr_irq_auto_masklsw_set(self, aq_nic_cfg->aq_hw_caps->irq_mask);
 
        /* Interrupts */
-       reg_gen_irq_map_set(self,
-                           ((HW_ATL_B0_ERR_INT << 0x18) | (1U << 0x1F)) |
+       hw_atl_reg_gen_irq_map_set(self,
+                                  ((HW_ATL_B0_ERR_INT << 0x18) | (1U << 0x1F)) |
                            ((HW_ATL_B0_ERR_INT << 0x10) | (1U << 0x17)), 0U);
 
        hw_atl_b0_hw_offload_set(self, aq_nic_cfg);
@@ -421,28 +426,28 @@ err_exit:
 static int hw_atl_b0_hw_ring_tx_start(struct aq_hw_s *self,
                                      struct aq_ring_s *ring)
 {
-       tdm_tx_desc_en_set(self, 1, ring->idx);
+       hw_atl_tdm_tx_desc_en_set(self, 1, ring->idx);
        return aq_hw_err_from_flags(self);
 }
 
 static int hw_atl_b0_hw_ring_rx_start(struct aq_hw_s *self,
                                      struct aq_ring_s *ring)
 {
-       rdm_rx_desc_en_set(self, 1, ring->idx);
+       hw_atl_rdm_rx_desc_en_set(self, 1, ring->idx);
        return aq_hw_err_from_flags(self);
 }
 
 static int hw_atl_b0_hw_start(struct aq_hw_s *self)
 {
-       tpb_tx_buff_en_set(self, 1);
-       rpb_rx_buff_en_set(self, 1);
+       hw_atl_tpb_tx_buff_en_set(self, 1);
+       hw_atl_rpb_rx_buff_en_set(self, 1);
        return aq_hw_err_from_flags(self);
 }
 
 static int hw_atl_b0_hw_tx_ring_tail_update(struct aq_hw_s *self,
                                            struct aq_ring_s *ring)
 {
-       reg_tx_dma_desc_tail_ptr_set(self, ring->sw_tail, ring->idx);
+       hw_atl_reg_tx_dma_desc_tail_ptr_set(self, ring->sw_tail, ring->idx);
        return 0;
 }
 
@@ -528,36 +533,36 @@ static int hw_atl_b0_hw_ring_rx_init(struct aq_hw_s *self,
        u32 dma_desc_addr_lsw = (u32)aq_ring->dx_ring_pa;
        u32 dma_desc_addr_msw = (u32)(((u64)aq_ring->dx_ring_pa) >> 32);
 
-       rdm_rx_desc_en_set(self, false, aq_ring->idx);
+       hw_atl_rdm_rx_desc_en_set(self, false, aq_ring->idx);
 
-       rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx);
+       hw_atl_rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx);
 
-       reg_rx_dma_desc_base_addresslswset(self, dma_desc_addr_lsw,
-                                          aq_ring->idx);
+       hw_atl_reg_rx_dma_desc_base_addresslswset(self, dma_desc_addr_lsw,
+                                                 aq_ring->idx);
 
-       reg_rx_dma_desc_base_addressmswset(self,
-                                          dma_desc_addr_msw, aq_ring->idx);
+       hw_atl_reg_rx_dma_desc_base_addressmswset(self,
+                                                 dma_desc_addr_msw, aq_ring->idx);
 
-       rdm_rx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx);
+       hw_atl_rdm_rx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx);
 
-       rdm_rx_desc_data_buff_size_set(self,
-                                      AQ_CFG_RX_FRAME_MAX / 1024U,
+       hw_atl_rdm_rx_desc_data_buff_size_set(self,
+                                             AQ_CFG_RX_FRAME_MAX / 1024U,
                                       aq_ring->idx);
 
-       rdm_rx_desc_head_buff_size_set(self, 0U, aq_ring->idx);
-       rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx);
-       rpo_rx_desc_vlan_stripping_set(self, 0U, aq_ring->idx);
+       hw_atl_rdm_rx_desc_head_buff_size_set(self, 0U, aq_ring->idx);
+       hw_atl_rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx);
+       hw_atl_rpo_rx_desc_vlan_stripping_set(self, 0U, aq_ring->idx);
 
        /* Rx ring set mode */
 
        /* Mapping interrupt vector */
-       itr_irq_map_rx_set(self, aq_ring_param->vec_idx, aq_ring->idx);
-       itr_irq_map_en_rx_set(self, true, aq_ring->idx);
+       hw_atl_itr_irq_map_rx_set(self, aq_ring_param->vec_idx, aq_ring->idx);
+       hw_atl_itr_irq_map_en_rx_set(self, true, aq_ring->idx);
 
-       rdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx);
-       rdm_rx_desc_dca_en_set(self, 0U, aq_ring->idx);
-       rdm_rx_head_dca_en_set(self, 0U, aq_ring->idx);
-       rdm_rx_pld_dca_en_set(self, 0U, aq_ring->idx);
+       hw_atl_rdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx);
+       hw_atl_rdm_rx_desc_dca_en_set(self, 0U, aq_ring->idx);
+       hw_atl_rdm_rx_head_dca_en_set(self, 0U, aq_ring->idx);
+       hw_atl_rdm_rx_pld_dca_en_set(self, 0U, aq_ring->idx);
 
        return aq_hw_err_from_flags(self);
 }
@@ -569,25 +574,25 @@ static int hw_atl_b0_hw_ring_tx_init(struct aq_hw_s *self,
        u32 dma_desc_lsw_addr = (u32)aq_ring->dx_ring_pa;
        u32 dma_desc_msw_addr = (u32)(((u64)aq_ring->dx_ring_pa) >> 32);
 
-       reg_tx_dma_desc_base_addresslswset(self, dma_desc_lsw_addr,
-                                          aq_ring->idx);
+       hw_atl_reg_tx_dma_desc_base_addresslswset(self, dma_desc_lsw_addr,
+                                                 aq_ring->idx);
 
-       reg_tx_dma_desc_base_addressmswset(self, dma_desc_msw_addr,
-                                          aq_ring->idx);
+       hw_atl_reg_tx_dma_desc_base_addressmswset(self, dma_desc_msw_addr,
+                                                 aq_ring->idx);
 
-       tdm_tx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx);
+       hw_atl_tdm_tx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx);
 
        hw_atl_b0_hw_tx_ring_tail_update(self, aq_ring);
 
        /* Set Tx threshold */
-       tdm_tx_desc_wr_wb_threshold_set(self, 0U, aq_ring->idx);
+       hw_atl_tdm_tx_desc_wr_wb_threshold_set(self, 0U, aq_ring->idx);
 
        /* Mapping interrupt vector */
-       itr_irq_map_tx_set(self, aq_ring_param->vec_idx, aq_ring->idx);
-       itr_irq_map_en_tx_set(self, true, aq_ring->idx);
+       hw_atl_itr_irq_map_tx_set(self, aq_ring_param->vec_idx, aq_ring->idx);
+       hw_atl_itr_irq_map_en_tx_set(self, true, aq_ring->idx);
 
-       tdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx);
-       tdm_tx_desc_dca_en_set(self, 0U, aq_ring->idx);
+       hw_atl_tdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx);
+       hw_atl_tdm_tx_desc_dca_en_set(self, 0U, aq_ring->idx);
 
        return aq_hw_err_from_flags(self);
 }
@@ -608,7 +613,7 @@ static int hw_atl_b0_hw_ring_rx_fill(struct aq_hw_s *self,
                rxd->hdr_addr = 0U;
        }
 
-       reg_rx_dma_desc_tail_ptr_set(self, sw_tail_old, ring->idx);
+       hw_atl_reg_rx_dma_desc_tail_ptr_set(self, sw_tail_old, ring->idx);
 
        return aq_hw_err_from_flags(self);
 }
@@ -617,7 +622,7 @@ static int hw_atl_b0_hw_ring_tx_head_update(struct aq_hw_s *self,
                                            struct aq_ring_s *ring)
 {
        int err = 0;
-       unsigned int hw_head_ = tdm_tx_desc_head_ptr_get(self, ring->idx);
+       unsigned int hw_head_ = hw_atl_tdm_tx_desc_head_ptr_get(self, ring->idx);
 
        if (aq_utils_obj_test(&self->flags, AQ_HW_FLAG_ERR_UNPLUG)) {
                err = -ENXIO;
@@ -722,14 +727,14 @@ static int hw_atl_b0_hw_ring_rx_receive(struct aq_hw_s *self,
 
 static int hw_atl_b0_hw_irq_enable(struct aq_hw_s *self, u64 mask)
 {
-       itr_irq_msk_setlsw_set(self, LODWORD(mask));
+       hw_atl_itr_irq_msk_setlsw_set(self, LODWORD(mask));
        return aq_hw_err_from_flags(self);
 }
 
 static int hw_atl_b0_hw_irq_disable(struct aq_hw_s *self, u64 mask)
 {
-       itr_irq_msk_clearlsw_set(self, LODWORD(mask));
-       itr_irq_status_clearlsw_set(self, LODWORD(mask));
+       hw_atl_itr_irq_msk_clearlsw_set(self, LODWORD(mask));
+       hw_atl_itr_irq_status_clearlsw_set(self, LODWORD(mask));
 
        atomic_inc(&self->dpc);
        return aq_hw_err_from_flags(self);
@@ -737,7 +742,7 @@ static int hw_atl_b0_hw_irq_disable(struct aq_hw_s *self, u64 mask)
 
 static int hw_atl_b0_hw_irq_read(struct aq_hw_s *self, u64 *mask)
 {
-       *mask = itr_irq_statuslsw_get(self);
+       *mask = hw_atl_itr_irq_statuslsw_get(self);
        return aq_hw_err_from_flags(self);
 }
 
@@ -748,20 +753,20 @@ static int hw_atl_b0_hw_packet_filter_set(struct aq_hw_s *self,
 {
        unsigned int i = 0U;
 
-       rpfl2promiscuous_mode_en_set(self, IS_FILTER_ENABLED(IFF_PROMISC));
-       rpfl2multicast_flr_en_set(self,
-                                 IS_FILTER_ENABLED(IFF_MULTICAST), 0);
+       hw_atl_rpfl2promiscuous_mode_en_set(self, IS_FILTER_ENABLED(IFF_PROMISC));
+       hw_atl_rpfl2multicast_flr_en_set(self,
+                                        IS_FILTER_ENABLED(IFF_MULTICAST), 0);
 
-       rpfl2_accept_all_mc_packets_set(self,
-                                       IS_FILTER_ENABLED(IFF_ALLMULTI));
+       hw_atl_rpfl2_accept_all_mc_packets_set(self,
+                                              IS_FILTER_ENABLED(IFF_ALLMULTI));
 
-       rpfl2broadcast_en_set(self, IS_FILTER_ENABLED(IFF_BROADCAST));
+       hw_atl_rpfl2broadcast_en_set(self, IS_FILTER_ENABLED(IFF_BROADCAST));
 
        self->aq_nic_cfg->is_mc_list_enabled = IS_FILTER_ENABLED(IFF_MULTICAST);
 
        for (i = HW_ATL_B0_MAC_MIN; i < HW_ATL_B0_MAC_MAX; ++i)
-               rpfl2_uc_flr_en_set(self,
-                                   (self->aq_nic_cfg->is_mc_list_enabled &&
+               hw_atl_rpfl2_uc_flr_en_set(self,
+                                          (self->aq_nic_cfg->is_mc_list_enabled &&
                                    (i <= self->aq_nic_cfg->mc_list_count)) ?
                                    1U : 0U, i);
 
@@ -790,16 +795,16 @@ static int hw_atl_b0_hw_multicast_list_set(struct aq_hw_s *self,
                u32 l = (ar_mac[i][2] << 24) | (ar_mac[i][3] << 16) |
                                        (ar_mac[i][4] << 8) | ar_mac[i][5];
 
-               rpfl2_uc_flr_en_set(self, 0U, HW_ATL_B0_MAC_MIN + i);
+               hw_atl_rpfl2_uc_flr_en_set(self, 0U, HW_ATL_B0_MAC_MIN + i);
 
-               rpfl2unicast_dest_addresslsw_set(self,
-                                                l, HW_ATL_B0_MAC_MIN + i);
+               hw_atl_rpfl2unicast_dest_addresslsw_set(self,
+                                                       l, HW_ATL_B0_MAC_MIN + i);
 
-               rpfl2unicast_dest_addressmsw_set(self,
-                                                h, HW_ATL_B0_MAC_MIN + i);
+               hw_atl_rpfl2unicast_dest_addressmsw_set(self,
+                                                       h, HW_ATL_B0_MAC_MIN + i);
 
-               rpfl2_uc_flr_en_set(self,
-                                   (self->aq_nic_cfg->is_mc_list_enabled),
+               hw_atl_rpfl2_uc_flr_en_set(self,
+                                          (self->aq_nic_cfg->is_mc_list_enabled),
                                    HW_ATL_B0_MAC_MIN + i);
        }
 
@@ -818,10 +823,10 @@ static int hw_atl_b0_hw_interrupt_moderation_set(struct aq_hw_s *self)
        switch (self->aq_nic_cfg->itr) {
        case  AQ_CFG_INTERRUPT_MODERATION_ON:
        case  AQ_CFG_INTERRUPT_MODERATION_AUTO:
-               tdm_tx_desc_wr_wb_irq_en_set(self, 0U);
-               tdm_tdm_intr_moder_en_set(self, 1U);
-               rdm_rx_desc_wr_wb_irq_en_set(self, 0U);
-               rdm_rdm_intr_moder_en_set(self, 1U);
+               hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 0U);
+               hw_atl_tdm_tdm_intr_moder_en_set(self, 1U);
+               hw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 0U);
+               hw_atl_rdm_rdm_intr_moder_en_set(self, 1U);
 
                if (self->aq_nic_cfg->itr == AQ_CFG_INTERRUPT_MODERATION_ON) {
                        /* HW timers are in 2us units */
@@ -881,18 +886,18 @@ static int hw_atl_b0_hw_interrupt_moderation_set(struct aq_hw_s *self)
                }
                break;
        case AQ_CFG_INTERRUPT_MODERATION_OFF:
-               tdm_tx_desc_wr_wb_irq_en_set(self, 1U);
-               tdm_tdm_intr_moder_en_set(self, 0U);
-               rdm_rx_desc_wr_wb_irq_en_set(self, 1U);
-               rdm_rdm_intr_moder_en_set(self, 0U);
+               hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 1U);
+               hw_atl_tdm_tdm_intr_moder_en_set(self, 0U);
+               hw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 1U);
+               hw_atl_rdm_rdm_intr_moder_en_set(self, 0U);
                itr_tx = 0U;
                itr_rx = 0U;
                break;
        }
 
        for (i = HW_ATL_B0_RINGS_MAX; i--;) {
-               reg_tx_intr_moder_ctrl_set(self, itr_tx, i);
-               reg_rx_intr_moder_ctrl_set(self, itr_rx, i);
+               hw_atl_reg_tx_intr_moder_ctrl_set(self, itr_tx, i);
+               hw_atl_reg_rx_intr_moder_ctrl_set(self, itr_rx, i);
        }
 
        return aq_hw_err_from_flags(self);
@@ -907,14 +912,14 @@ static int hw_atl_b0_hw_stop(struct aq_hw_s *self)
 static int hw_atl_b0_hw_ring_tx_stop(struct aq_hw_s *self,
                                     struct aq_ring_s *ring)
 {
-       tdm_tx_desc_en_set(self, 0U, ring->idx);
+       hw_atl_tdm_tx_desc_en_set(self, 0U, ring->idx);
        return aq_hw_err_from_flags(self);
 }
 
 static int hw_atl_b0_hw_ring_rx_stop(struct aq_hw_s *self,
                                     struct aq_ring_s *ring)
 {
-       rdm_rx_desc_en_set(self, 0U, ring->idx);
+       hw_atl_rdm_rx_desc_en_set(self, 0U, ring->idx);
        return aq_hw_err_from_flags(self);
 }
 
index 2f21fe6fd6baeaf653772aefd73d1f11376eb65b..10ba035dadb19c8ffa0409d9ed636009695265b5 100644 (file)
 #include "../aq_hw_utils.h"
 
 /* global */
-void reg_glb_cpu_sem_set(struct aq_hw_s *aq_hw, u32 glb_cpu_sem, u32 semaphore)
+void hw_atl_reg_glb_cpu_sem_set(struct aq_hw_s *aq_hw, u32 glb_cpu_sem,
+                               u32 semaphore)
 {
        aq_hw_write_reg(aq_hw, HW_ATL_GLB_CPU_SEM_ADR(semaphore), glb_cpu_sem);
 }
 
-u32 reg_glb_cpu_sem_get(struct aq_hw_s *aq_hw, u32 semaphore)
+u32 hw_atl_reg_glb_cpu_sem_get(struct aq_hw_s *aq_hw, u32 semaphore)
 {
        return aq_hw_read_reg(aq_hw, HW_ATL_GLB_CPU_SEM_ADR(semaphore));
 }
 
-void glb_glb_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 glb_reg_res_dis)
+void hw_atl_glb_glb_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 glb_reg_res_dis)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_GLB_REG_RES_DIS_ADR,
                            HW_ATL_GLB_REG_RES_DIS_MSK,
@@ -34,83 +35,85 @@ void glb_glb_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 glb_reg_res_dis)
                            glb_reg_res_dis);
 }
 
-void glb_soft_res_set(struct aq_hw_s *aq_hw, u32 soft_res)
+void hw_atl_glb_soft_res_set(struct aq_hw_s *aq_hw, u32 soft_res)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_GLB_SOFT_RES_ADR,
                            HW_ATL_GLB_SOFT_RES_MSK,
                            HW_ATL_GLB_SOFT_RES_SHIFT, soft_res);
 }
 
-u32 glb_soft_res_get(struct aq_hw_s *aq_hw)
+u32 hw_atl_glb_soft_res_get(struct aq_hw_s *aq_hw)
 {
        return aq_hw_read_reg_bit(aq_hw, HW_ATL_GLB_SOFT_RES_ADR,
                                  HW_ATL_GLB_SOFT_RES_MSK,
                                  HW_ATL_GLB_SOFT_RES_SHIFT);
 }
 
-u32 reg_rx_dma_stat_counter7get(struct aq_hw_s *aq_hw)
+u32 hw_atl_reg_rx_dma_stat_counter7get(struct aq_hw_s *aq_hw)
 {
        return aq_hw_read_reg(aq_hw, HW_ATL_RX_DMA_STAT_COUNTER7_ADR);
 }
 
-u32 reg_glb_mif_id_get(struct aq_hw_s *aq_hw)
+u32 hw_atl_reg_glb_mif_id_get(struct aq_hw_s *aq_hw)
 {
        return aq_hw_read_reg(aq_hw, HW_ATL_GLB_MIF_ID_ADR);
 }
 
 /* stats */
-u32 rpb_rx_dma_drop_pkt_cnt_get(struct aq_hw_s *aq_hw)
+u32 hw_atl_rpb_rx_dma_drop_pkt_cnt_get(struct aq_hw_s *aq_hw)
 {
        return aq_hw_read_reg(aq_hw, HW_ATL_RPB_RX_DMA_DROP_PKT_CNT_ADR);
 }
 
-u32 stats_rx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw)
+u32 hw_atl_stats_rx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw)
 {
        return aq_hw_read_reg(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERLSW);
 }
 
-u32 stats_rx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw)
+u32 hw_atl_stats_rx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw)
 {
        return aq_hw_read_reg(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERLSW);
 }
 
-u32 stats_tx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw)
+u32 hw_atl_stats_tx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw)
 {
        return aq_hw_read_reg(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERLSW);
 }
 
-u32 stats_tx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw)
+u32 hw_atl_stats_tx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw)
 {
        return aq_hw_read_reg(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERLSW);
 }
 
-u32 stats_rx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw)
+u32 hw_atl_stats_rx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw)
 {
        return aq_hw_read_reg(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERMSW);
 }
 
-u32 stats_rx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw)
+u32 hw_atl_stats_rx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw)
 {
        return aq_hw_read_reg(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERMSW);
 }
 
-u32 stats_tx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw)
+u32 hw_atl_stats_tx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw)
 {
        return aq_hw_read_reg(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERMSW);
 }
 
-u32 stats_tx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw)
+u32 hw_atl_stats_tx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw)
 {
        return aq_hw_read_reg(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERMSW);
 }
 
 /* interrupt */
-void itr_irq_auto_masklsw_set(struct aq_hw_s *aq_hw, u32 irq_auto_masklsw)
+void hw_atl_itr_irq_auto_masklsw_set(struct aq_hw_s *aq_hw,
+                                    u32 irq_auto_masklsw)
 {
        aq_hw_write_reg(aq_hw, HW_ATL_ITR_IAMRLSW_ADR, irq_auto_masklsw);
 }
 
-void itr_irq_map_en_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_rx, u32 rx)
+void hw_atl_itr_irq_map_en_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_rx,
+                                 u32 rx)
 {
 /* register address for bitfield imr_rx{r}_en */
        static u32 itr_imr_rxren_adr[32] = {
@@ -150,7 +153,8 @@ void itr_irq_map_en_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_rx, u32 rx)
                            irq_map_en_rx);
 }
 
-void itr_irq_map_en_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_tx, u32 tx)
+void hw_atl_itr_irq_map_en_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_tx,
+                                 u32 tx)
 {
 /* register address for bitfield imr_tx{t}_en */
        static u32 itr_imr_txten_adr[32] = {
@@ -190,7 +194,7 @@ void itr_irq_map_en_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_tx, u32 tx)
                            irq_map_en_tx);
 }
 
-void itr_irq_map_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_rx, u32 rx)
+void hw_atl_itr_irq_map_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_rx, u32 rx)
 {
 /* register address for bitfield imr_rx{r}[4:0] */
        static u32 itr_imr_rxr_adr[32] = {
@@ -230,7 +234,7 @@ void itr_irq_map_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_rx, u32 rx)
                            irq_map_rx);
 }
 
-void itr_irq_map_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_tx, u32 tx)
+void hw_atl_itr_irq_map_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_tx, u32 tx)
 {
 /* register address for bitfield imr_tx{t}[4:0] */
        static u32 itr_imr_txt_adr[32] = {
@@ -270,69 +274,71 @@ void itr_irq_map_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_tx, u32 tx)
                            irq_map_tx);
 }
 
-void itr_irq_msk_clearlsw_set(struct aq_hw_s *aq_hw, u32 irq_msk_clearlsw)
+void hw_atl_itr_irq_msk_clearlsw_set(struct aq_hw_s *aq_hw,
+                                    u32 irq_msk_clearlsw)
 {
        aq_hw_write_reg(aq_hw, HW_ATL_ITR_IMCRLSW_ADR, irq_msk_clearlsw);
 }
 
-void itr_irq_msk_setlsw_set(struct aq_hw_s *aq_hw, u32 irq_msk_setlsw)
+void hw_atl_itr_irq_msk_setlsw_set(struct aq_hw_s *aq_hw, u32 irq_msk_setlsw)
 {
        aq_hw_write_reg(aq_hw, HW_ATL_ITR_IMSRLSW_ADR, irq_msk_setlsw);
 }
 
-void itr_irq_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 irq_reg_res_dis)
+void hw_atl_itr_irq_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 irq_reg_res_dis)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_ITR_REG_RES_DSBL_ADR,
                            HW_ATL_ITR_REG_RES_DSBL_MSK,
                            HW_ATL_ITR_REG_RES_DSBL_SHIFT, irq_reg_res_dis);
 }
 
-void itr_irq_status_clearlsw_set(struct aq_hw_s *aq_hw,
-                                u32 irq_status_clearlsw)
+void hw_atl_itr_irq_status_clearlsw_set(struct aq_hw_s *aq_hw,
+                                       u32 irq_status_clearlsw)
 {
        aq_hw_write_reg(aq_hw, HW_ATL_ITR_ISCRLSW_ADR, irq_status_clearlsw);
 }
 
-u32 itr_irq_statuslsw_get(struct aq_hw_s *aq_hw)
+u32 hw_atl_itr_irq_statuslsw_get(struct aq_hw_s *aq_hw)
 {
        return aq_hw_read_reg(aq_hw, HW_ATL_ITR_ISRLSW_ADR);
 }
 
-u32 itr_res_irq_get(struct aq_hw_s *aq_hw)
+u32 hw_atl_itr_res_irq_get(struct aq_hw_s *aq_hw)
 {
        return aq_hw_read_reg_bit(aq_hw, HW_ATL_ITR_RES_ADR, HW_ATL_ITR_RES_MSK,
                                  HW_ATL_ITR_RES_SHIFT);
 }
 
-void itr_res_irq_set(struct aq_hw_s *aq_hw, u32 res_irq)
+void hw_atl_itr_res_irq_set(struct aq_hw_s *aq_hw, u32 res_irq)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_ITR_RES_ADR, HW_ATL_ITR_RES_MSK,
                            HW_ATL_ITR_RES_SHIFT, res_irq);
 }
 
 /* rdm */
-void rdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca)
+void hw_atl_rdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADCPUID_ADR(dca),
                            HW_ATL_RDM_DCADCPUID_MSK,
                            HW_ATL_RDM_DCADCPUID_SHIFT, cpuid);
 }
 
-void rdm_rx_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_dca_en)
+void hw_atl_rdm_rx_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_dca_en)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCA_EN_ADR, HW_ATL_RDM_DCA_EN_MSK,
                            HW_ATL_RDM_DCA_EN_SHIFT, rx_dca_en);
 }
 
-void rdm_rx_dca_mode_set(struct aq_hw_s *aq_hw, u32 rx_dca_mode)
+void hw_atl_rdm_rx_dca_mode_set(struct aq_hw_s *aq_hw, u32 rx_dca_mode)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCA_MODE_ADR,
                            HW_ATL_RDM_DCA_MODE_MSK,
                            HW_ATL_RDM_DCA_MODE_SHIFT, rx_dca_mode);
 }
 
-void rdm_rx_desc_data_buff_size_set(struct aq_hw_s *aq_hw,
-                                   u32 rx_desc_data_buff_size, u32 descriptor)
+void hw_atl_rdm_rx_desc_data_buff_size_set(struct aq_hw_s *aq_hw,
+                                          u32 rx_desc_data_buff_size,
+                                          u32 descriptor)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDDATA_SIZE_ADR(descriptor),
                            HW_ATL_RDM_DESCDDATA_SIZE_MSK,
@@ -340,7 +346,8 @@ void rdm_rx_desc_data_buff_size_set(struct aq_hw_s *aq_hw,
                            rx_desc_data_buff_size);
 }
 
-void rdm_rx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_dca_en, u32 dca)
+void hw_atl_rdm_rx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_dca_en,
+                                  u32 dca)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADDESC_EN_ADR(dca),
                            HW_ATL_RDM_DCADDESC_EN_MSK,
@@ -348,7 +355,8 @@ void rdm_rx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_dca_en, u32 dca)
                            rx_desc_dca_en);
 }
 
-void rdm_rx_desc_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_en, u32 descriptor)
+void hw_atl_rdm_rx_desc_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_en,
+                              u32 descriptor)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDEN_ADR(descriptor),
                            HW_ATL_RDM_DESCDEN_MSK,
@@ -356,8 +364,9 @@ void rdm_rx_desc_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_en, u32 descriptor)
                            rx_desc_en);
 }
 
-void rdm_rx_desc_head_buff_size_set(struct aq_hw_s *aq_hw,
-                                   u32 rx_desc_head_buff_size, u32 descriptor)
+void hw_atl_rdm_rx_desc_head_buff_size_set(struct aq_hw_s *aq_hw,
+                                          u32 rx_desc_head_buff_size,
+                                          u32 descriptor)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDHDR_SIZE_ADR(descriptor),
                            HW_ATL_RDM_DESCDHDR_SIZE_MSK,
@@ -365,8 +374,9 @@ void rdm_rx_desc_head_buff_size_set(struct aq_hw_s *aq_hw,
                            rx_desc_head_buff_size);
 }
 
-void rdm_rx_desc_head_splitting_set(struct aq_hw_s *aq_hw,
-                                   u32 rx_desc_head_splitting, u32 descriptor)
+void hw_atl_rdm_rx_desc_head_splitting_set(struct aq_hw_s *aq_hw,
+                                          u32 rx_desc_head_splitting,
+                                          u32 descriptor)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDHDR_SPLIT_ADR(descriptor),
                            HW_ATL_RDM_DESCDHDR_SPLIT_MSK,
@@ -374,21 +384,23 @@ void rdm_rx_desc_head_splitting_set(struct aq_hw_s *aq_hw,
                            rx_desc_head_splitting);
 }
 
-u32 rdm_rx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor)
+u32 hw_atl_rdm_rx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor)
 {
        return aq_hw_read_reg_bit(aq_hw, HW_ATL_RDM_DESCDHD_ADR(descriptor),
                                  HW_ATL_RDM_DESCDHD_MSK,
                                  HW_ATL_RDM_DESCDHD_SHIFT);
 }
 
-void rdm_rx_desc_len_set(struct aq_hw_s *aq_hw, u32 rx_desc_len, u32 descriptor)
+void hw_atl_rdm_rx_desc_len_set(struct aq_hw_s *aq_hw, u32 rx_desc_len,
+                               u32 descriptor)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDLEN_ADR(descriptor),
                            HW_ATL_RDM_DESCDLEN_MSK, HW_ATL_RDM_DESCDLEN_SHIFT,
                            rx_desc_len);
 }
 
-void rdm_rx_desc_res_set(struct aq_hw_s *aq_hw, u32 rx_desc_res, u32 descriptor)
+void hw_atl_rdm_rx_desc_res_set(struct aq_hw_s *aq_hw, u32 rx_desc_res,
+                               u32 descriptor)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDRESET_ADR(descriptor),
                            HW_ATL_RDM_DESCDRESET_MSK,
@@ -396,8 +408,8 @@ void rdm_rx_desc_res_set(struct aq_hw_s *aq_hw, u32 rx_desc_res, u32 descriptor)
                            rx_desc_res);
 }
 
-void rdm_rx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw,
-                                 u32 rx_desc_wr_wb_irq_en)
+void hw_atl_rdm_rx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw,
+                                        u32 rx_desc_wr_wb_irq_en)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_INT_DESC_WRB_EN_ADR,
                            HW_ATL_RDM_INT_DESC_WRB_EN_MSK,
@@ -405,7 +417,8 @@ void rdm_rx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw,
                            rx_desc_wr_wb_irq_en);
 }
 
-void rdm_rx_head_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_head_dca_en, u32 dca)
+void hw_atl_rdm_rx_head_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_head_dca_en,
+                                  u32 dca)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADHDR_EN_ADR(dca),
                            HW_ATL_RDM_DCADHDR_EN_MSK,
@@ -413,7 +426,8 @@ void rdm_rx_head_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_head_dca_en, u32 dca)
                            rx_head_dca_en);
 }
 
-void rdm_rx_pld_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_pld_dca_en, u32 dca)
+void hw_atl_rdm_rx_pld_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_pld_dca_en,
+                                 u32 dca)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADPAY_EN_ADR(dca),
                            HW_ATL_RDM_DCADPAY_EN_MSK,
@@ -421,7 +435,8 @@ void rdm_rx_pld_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_pld_dca_en, u32 dca)
                            rx_pld_dca_en);
 }
 
-void rdm_rdm_intr_moder_en_set(struct aq_hw_s *aq_hw, u32 rdm_intr_moder_en)
+void hw_atl_rdm_rdm_intr_moder_en_set(struct aq_hw_s *aq_hw,
+                                     u32 rdm_intr_moder_en)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_INT_RIM_EN_ADR,
                            HW_ATL_RDM_INT_RIM_EN_MSK,
@@ -430,132 +445,139 @@ void rdm_rdm_intr_moder_en_set(struct aq_hw_s *aq_hw, u32 rdm_intr_moder_en)
 }
 
 /* reg */
-void reg_gen_irq_map_set(struct aq_hw_s *aq_hw, u32 gen_intr_map, u32 regidx)
+void hw_atl_reg_gen_irq_map_set(struct aq_hw_s *aq_hw, u32 gen_intr_map,
+                               u32 regidx)
 {
        aq_hw_write_reg(aq_hw, HW_ATL_GEN_INTR_MAP_ADR(regidx), gen_intr_map);
 }
 
-u32 reg_gen_irq_status_get(struct aq_hw_s *aq_hw)
+u32 hw_atl_reg_gen_irq_status_get(struct aq_hw_s *aq_hw)
 {
        return aq_hw_read_reg(aq_hw, HW_ATL_GEN_INTR_STAT_ADR);
 }
 
-void reg_irq_glb_ctl_set(struct aq_hw_s *aq_hw, u32 intr_glb_ctl)
+void hw_atl_reg_irq_glb_ctl_set(struct aq_hw_s *aq_hw, u32 intr_glb_ctl)
 {
        aq_hw_write_reg(aq_hw, HW_ATL_INTR_GLB_CTL_ADR, intr_glb_ctl);
 }
 
-void reg_irq_thr_set(struct aq_hw_s *aq_hw, u32 intr_thr, u32 throttle)
+void hw_atl_reg_irq_thr_set(struct aq_hw_s *aq_hw, u32 intr_thr, u32 throttle)
 {
        aq_hw_write_reg(aq_hw, HW_ATL_INTR_THR_ADR(throttle), intr_thr);
 }
 
-void reg_rx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw,
-                                       u32 rx_dma_desc_base_addrlsw,
-                                       u32 descriptor)
+void hw_atl_reg_rx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw,
+                                              u32 rx_dma_desc_base_addrlsw,
+                                              u32 descriptor)
 {
        aq_hw_write_reg(aq_hw, HW_ATL_RX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor),
                        rx_dma_desc_base_addrlsw);
 }
 
-void reg_rx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw,
-                                       u32 rx_dma_desc_base_addrmsw,
-                                       u32 descriptor)
+void hw_atl_reg_rx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw,
+                                              u32 rx_dma_desc_base_addrmsw,
+                                              u32 descriptor)
 {
        aq_hw_write_reg(aq_hw, HW_ATL_RX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor),
                        rx_dma_desc_base_addrmsw);
 }
 
-u32 reg_rx_dma_desc_status_get(struct aq_hw_s *aq_hw, u32 descriptor)
+u32 hw_atl_reg_rx_dma_desc_status_get(struct aq_hw_s *aq_hw, u32 descriptor)
 {
        return aq_hw_read_reg(aq_hw, HW_ATL_RX_DMA_DESC_STAT_ADR(descriptor));
 }
 
-void reg_rx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw,
-                                 u32 rx_dma_desc_tail_ptr, u32 descriptor)
+void hw_atl_reg_rx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw,
+                                        u32 rx_dma_desc_tail_ptr,
+                                        u32 descriptor)
 {
        aq_hw_write_reg(aq_hw, HW_ATL_RX_DMA_DESC_TAIL_PTR_ADR(descriptor),
                        rx_dma_desc_tail_ptr);
 }
 
-void reg_rx_flr_mcst_flr_msk_set(struct aq_hw_s *aq_hw, u32 rx_flr_mcst_flr_msk)
+void hw_atl_reg_rx_flr_mcst_flr_msk_set(struct aq_hw_s *aq_hw,
+                                       u32 rx_flr_mcst_flr_msk)
 {
        aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_MCST_FLR_MSK_ADR,
                        rx_flr_mcst_flr_msk);
 }
 
-void reg_rx_flr_mcst_flr_set(struct aq_hw_s *aq_hw, u32 rx_flr_mcst_flr,
-                            u32 filter)
+void hw_atl_reg_rx_flr_mcst_flr_set(struct aq_hw_s *aq_hw, u32 rx_flr_mcst_flr,
+                                   u32 filter)
 {
        aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_MCST_FLR_ADR(filter),
                        rx_flr_mcst_flr);
 }
 
-void reg_rx_flr_rss_control1set(struct aq_hw_s *aq_hw, u32 rx_flr_rss_control1)
+void hw_atl_reg_rx_flr_rss_control1set(struct aq_hw_s *aq_hw,
+                                      u32 rx_flr_rss_control1)
 {
        aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_RSS_CONTROL1_ADR,
                        rx_flr_rss_control1);
 }
 
-void reg_rx_flr_control2_set(struct aq_hw_s *aq_hw, u32 rx_filter_control2)
+void hw_atl_reg_rx_flr_control2_set(struct aq_hw_s *aq_hw,
+                                   u32 rx_filter_control2)
 {
        aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_CONTROL2_ADR, rx_filter_control2);
 }
 
-void reg_rx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw,
-                               u32 rx_intr_moderation_ctl,
-                               u32 queue)
+void hw_atl_reg_rx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw,
+                                      u32 rx_intr_moderation_ctl,
+                                      u32 queue)
 {
        aq_hw_write_reg(aq_hw, HW_ATL_RX_INTR_MODERATION_CTL_ADR(queue),
                        rx_intr_moderation_ctl);
 }
 
-void reg_tx_dma_debug_ctl_set(struct aq_hw_s *aq_hw, u32 tx_dma_debug_ctl)
+void hw_atl_reg_tx_dma_debug_ctl_set(struct aq_hw_s *aq_hw,
+                                    u32 tx_dma_debug_ctl)
 {
        aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DEBUG_CTL_ADR, tx_dma_debug_ctl);
 }
 
-void reg_tx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw,
-                                       u32 tx_dma_desc_base_addrlsw,
-                                       u32 descriptor)
+void hw_atl_reg_tx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw,
+                                              u32 tx_dma_desc_base_addrlsw,
+                                              u32 descriptor)
 {
        aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor),
                        tx_dma_desc_base_addrlsw);
 }
 
-void reg_tx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw,
-                                       u32 tx_dma_desc_base_addrmsw,
-                                       u32 descriptor)
+void hw_atl_reg_tx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw,
+                                              u32 tx_dma_desc_base_addrmsw,
+                                              u32 descriptor)
 {
        aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor),
                        tx_dma_desc_base_addrmsw);
 }
 
-void reg_tx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw,
-                                 u32 tx_dma_desc_tail_ptr, u32 descriptor)
+void hw_atl_reg_tx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw,
+                                        u32 tx_dma_desc_tail_ptr,
+                                        u32 descriptor)
 {
        aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DESC_TAIL_PTR_ADR(descriptor),
                        tx_dma_desc_tail_ptr);
 }
 
-void reg_tx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw,
-                               u32 tx_intr_moderation_ctl,
-                               u32 queue)
+void hw_atl_reg_tx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw,
+                                      u32 tx_intr_moderation_ctl,
+                                      u32 queue)
 {
        aq_hw_write_reg(aq_hw, HW_ATL_TX_INTR_MODERATION_CTL_ADR(queue),
                        tx_intr_moderation_ctl);
 }
 
 /* RPB: rx packet buffer */
-void rpb_dma_sys_lbk_set(struct aq_hw_s *aq_hw, u32 dma_sys_lbk)
+void hw_atl_rpb_dma_sys_lbk_set(struct aq_hw_s *aq_hw, u32 dma_sys_lbk)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_DMA_SYS_LBK_ADR,
                            HW_ATL_RPB_DMA_SYS_LBK_MSK,
                            HW_ATL_RPB_DMA_SYS_LBK_SHIFT, dma_sys_lbk);
 }
 
-void rpb_rpf_rx_traf_class_mode_set(struct aq_hw_s *aq_hw,
-                                   u32 rx_traf_class_mode)
+void hw_atl_rpb_rpf_rx_traf_class_mode_set(struct aq_hw_s *aq_hw,
+                                          u32 rx_traf_class_mode)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RPF_RX_TC_MODE_ADR,
                            HW_ATL_RPB_RPF_RX_TC_MODE_MSK,
@@ -563,16 +585,16 @@ void rpb_rpf_rx_traf_class_mode_set(struct aq_hw_s *aq_hw,
                            rx_traf_class_mode);
 }
 
-void rpb_rx_buff_en_set(struct aq_hw_s *aq_hw, u32 rx_buff_en)
+void hw_atl_rpb_rx_buff_en_set(struct aq_hw_s *aq_hw, u32 rx_buff_en)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RX_BUF_EN_ADR,
                            HW_ATL_RPB_RX_BUF_EN_MSK,
                            HW_ATL_RPB_RX_BUF_EN_SHIFT, rx_buff_en);
 }
 
-void rpb_rx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw,
-                                        u32 rx_buff_hi_threshold_per_tc,
-                                        u32 buffer)
+void hw_atl_rpb_rx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw,
+                                               u32 rx_buff_hi_threshold_per_tc,
+                                               u32 buffer)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBHI_THRESH_ADR(buffer),
                            HW_ATL_RPB_RXBHI_THRESH_MSK,
@@ -580,9 +602,9 @@ void rpb_rx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw,
                            rx_buff_hi_threshold_per_tc);
 }
 
-void rpb_rx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw,
-                                        u32 rx_buff_lo_threshold_per_tc,
-                                        u32 buffer)
+void hw_atl_rpb_rx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw,
+                                               u32 rx_buff_lo_threshold_per_tc,
+                                               u32 buffer)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBLO_THRESH_ADR(buffer),
                            HW_ATL_RPB_RXBLO_THRESH_MSK,
@@ -590,15 +612,15 @@ void rpb_rx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw,
                            rx_buff_lo_threshold_per_tc);
 }
 
-void rpb_rx_flow_ctl_mode_set(struct aq_hw_s *aq_hw, u32 rx_flow_ctl_mode)
+void hw_atl_rpb_rx_flow_ctl_mode_set(struct aq_hw_s *aq_hw, u32 rx_flow_ctl_mode)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RX_FC_MODE_ADR,
                            HW_ATL_RPB_RX_FC_MODE_MSK,
                            HW_ATL_RPB_RX_FC_MODE_SHIFT, rx_flow_ctl_mode);
 }
 
-void rpb_rx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
-                                    u32 rx_pkt_buff_size_per_tc, u32 buffer)
+void hw_atl_rpb_rx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
+                                           u32 rx_pkt_buff_size_per_tc, u32 buffer)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBBUF_SIZE_ADR(buffer),
                            HW_ATL_RPB_RXBBUF_SIZE_MSK,
@@ -606,8 +628,8 @@ void rpb_rx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
                            rx_pkt_buff_size_per_tc);
 }
 
-void rpb_rx_xoff_en_per_tc_set(struct aq_hw_s *aq_hw, u32 rx_xoff_en_per_tc,
-                              u32 buffer)
+void hw_atl_rpb_rx_xoff_en_per_tc_set(struct aq_hw_s *aq_hw, u32 rx_xoff_en_per_tc,
+                                     u32 buffer)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBXOFF_EN_ADR(buffer),
                            HW_ATL_RPB_RXBXOFF_EN_MSK,
@@ -617,8 +639,8 @@ void rpb_rx_xoff_en_per_tc_set(struct aq_hw_s *aq_hw, u32 rx_xoff_en_per_tc,
 
 /* rpf */
 
-void rpfl2broadcast_count_threshold_set(struct aq_hw_s *aq_hw,
-                                       u32 l2broadcast_count_threshold)
+void hw_atl_rpfl2broadcast_count_threshold_set(struct aq_hw_s *aq_hw,
+                                              u32 l2broadcast_count_threshold)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2BC_THRESH_ADR,
                            HW_ATL_RPFL2BC_THRESH_MSK,
@@ -626,29 +648,31 @@ void rpfl2broadcast_count_threshold_set(struct aq_hw_s *aq_hw,
                            l2broadcast_count_threshold);
 }
 
-void rpfl2broadcast_en_set(struct aq_hw_s *aq_hw, u32 l2broadcast_en)
+void hw_atl_rpfl2broadcast_en_set(struct aq_hw_s *aq_hw, u32 l2broadcast_en)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2BC_EN_ADR, HW_ATL_RPFL2BC_EN_MSK,
                            HW_ATL_RPFL2BC_EN_SHIFT, l2broadcast_en);
 }
 
-void rpfl2broadcast_flr_act_set(struct aq_hw_s *aq_hw, u32 l2broadcast_flr_act)
+void hw_atl_rpfl2broadcast_flr_act_set(struct aq_hw_s *aq_hw,
+                                      u32 l2broadcast_flr_act)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2BC_ACT_ADR,
                            HW_ATL_RPFL2BC_ACT_MSK,
                            HW_ATL_RPFL2BC_ACT_SHIFT, l2broadcast_flr_act);
 }
 
-void rpfl2multicast_flr_en_set(struct aq_hw_s *aq_hw, u32 l2multicast_flr_en,
-                              u32 filter)
+void hw_atl_rpfl2multicast_flr_en_set(struct aq_hw_s *aq_hw,
+                                     u32 l2multicast_flr_en,
+                                     u32 filter)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2MC_ENF_ADR(filter),
                            HW_ATL_RPFL2MC_ENF_MSK,
                            HW_ATL_RPFL2MC_ENF_SHIFT, l2multicast_flr_en);
 }
 
-void rpfl2promiscuous_mode_en_set(struct aq_hw_s *aq_hw,
-                                 u32 l2promiscuous_mode_en)
+void hw_atl_rpfl2promiscuous_mode_en_set(struct aq_hw_s *aq_hw,
+                                        u32 l2promiscuous_mode_en)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2PROMIS_MODE_ADR,
                            HW_ATL_RPFL2PROMIS_MODE_MSK,
@@ -656,33 +680,34 @@ void rpfl2promiscuous_mode_en_set(struct aq_hw_s *aq_hw,
                            l2promiscuous_mode_en);
 }
 
-void rpfl2unicast_flr_act_set(struct aq_hw_s *aq_hw, u32 l2unicast_flr_act,
-                             u32 filter)
+void hw_atl_rpfl2unicast_flr_act_set(struct aq_hw_s *aq_hw,
+                                    u32 l2unicast_flr_act,
+                                    u32 filter)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2UC_ACTF_ADR(filter),
                            HW_ATL_RPFL2UC_ACTF_MSK, HW_ATL_RPFL2UC_ACTF_SHIFT,
                            l2unicast_flr_act);
 }
 
-void rpfl2_uc_flr_en_set(struct aq_hw_s *aq_hw, u32 l2unicast_flr_en,
-                        u32 filter)
+void hw_atl_rpfl2_uc_flr_en_set(struct aq_hw_s *aq_hw, u32 l2unicast_flr_en,
+                               u32 filter)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2UC_ENF_ADR(filter),
                            HW_ATL_RPFL2UC_ENF_MSK,
                            HW_ATL_RPFL2UC_ENF_SHIFT, l2unicast_flr_en);
 }
 
-void rpfl2unicast_dest_addresslsw_set(struct aq_hw_s *aq_hw,
-                                     u32 l2unicast_dest_addresslsw,
-                                     u32 filter)
+void hw_atl_rpfl2unicast_dest_addresslsw_set(struct aq_hw_s *aq_hw,
+                                            u32 l2unicast_dest_addresslsw,
+                                            u32 filter)
 {
        aq_hw_write_reg(aq_hw, HW_ATL_RPFL2UC_DAFLSW_ADR(filter),
                        l2unicast_dest_addresslsw);
 }
 
-void rpfl2unicast_dest_addressmsw_set(struct aq_hw_s *aq_hw,
-                                     u32 l2unicast_dest_addressmsw,
-                                     u32 filter)
+void hw_atl_rpfl2unicast_dest_addressmsw_set(struct aq_hw_s *aq_hw,
+                                            u32 l2unicast_dest_addressmsw,
+                                            u32 filter)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2UC_DAFMSW_ADR(filter),
                            HW_ATL_RPFL2UC_DAFMSW_MSK,
@@ -690,8 +715,8 @@ void rpfl2unicast_dest_addressmsw_set(struct aq_hw_s *aq_hw,
                            l2unicast_dest_addressmsw);
 }
 
-void rpfl2_accept_all_mc_packets_set(struct aq_hw_s *aq_hw,
-                                    u32 l2_accept_all_mc_packets)
+void hw_atl_rpfl2_accept_all_mc_packets_set(struct aq_hw_s *aq_hw,
+                                           u32 l2_accept_all_mc_packets)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2MC_ACCEPT_ALL_ADR,
                            HW_ATL_RPFL2MC_ACCEPT_ALL_MSK,
@@ -699,8 +724,8 @@ void rpfl2_accept_all_mc_packets_set(struct aq_hw_s *aq_hw,
                            l2_accept_all_mc_packets);
 }
 
-void rpf_rpb_user_priority_tc_map_set(struct aq_hw_s *aq_hw,
-                                     u32 user_priority_tc_map, u32 tc)
+void hw_atl_rpf_rpb_user_priority_tc_map_set(struct aq_hw_s *aq_hw,
+                                            u32 user_priority_tc_map, u32 tc)
 {
 /* register address for bitfield rx_tc_up{t}[2:0] */
        static u32 rpf_rpb_rx_tc_upt_adr[8] = {
@@ -725,7 +750,7 @@ void rpf_rpb_user_priority_tc_map_set(struct aq_hw_s *aq_hw,
                            user_priority_tc_map);
 }
 
-void rpf_rss_key_addr_set(struct aq_hw_s *aq_hw, u32 rss_key_addr)
+void hw_atl_rpf_rss_key_addr_set(struct aq_hw_s *aq_hw, u32 rss_key_addr)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_KEY_ADDR_ADR,
                            HW_ATL_RPF_RSS_KEY_ADDR_MSK,
@@ -733,20 +758,20 @@ void rpf_rss_key_addr_set(struct aq_hw_s *aq_hw, u32 rss_key_addr)
                            rss_key_addr);
 }
 
-void rpf_rss_key_wr_data_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_data)
+void hw_atl_rpf_rss_key_wr_data_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_data)
 {
        aq_hw_write_reg(aq_hw, HW_ATL_RPF_RSS_KEY_WR_DATA_ADR,
                        rss_key_wr_data);
 }
 
-u32 rpf_rss_key_wr_en_get(struct aq_hw_s *aq_hw)
+u32 hw_atl_rpf_rss_key_wr_en_get(struct aq_hw_s *aq_hw)
 {
        return aq_hw_read_reg_bit(aq_hw, HW_ATL_RPF_RSS_KEY_WR_ENI_ADR,
                                  HW_ATL_RPF_RSS_KEY_WR_ENI_MSK,
                                  HW_ATL_RPF_RSS_KEY_WR_ENI_SHIFT);
 }
 
-void rpf_rss_key_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_en)
+void hw_atl_rpf_rss_key_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_en)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_KEY_WR_ENI_ADR,
                            HW_ATL_RPF_RSS_KEY_WR_ENI_MSK,
@@ -754,7 +779,8 @@ void rpf_rss_key_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_en)
                            rss_key_wr_en);
 }
 
-void rpf_rss_redir_tbl_addr_set(struct aq_hw_s *aq_hw, u32 rss_redir_tbl_addr)
+void hw_atl_rpf_rss_redir_tbl_addr_set(struct aq_hw_s *aq_hw,
+                                      u32 rss_redir_tbl_addr)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_ADDR_ADR,
                            HW_ATL_RPF_RSS_REDIR_ADDR_MSK,
@@ -762,8 +788,8 @@ void rpf_rss_redir_tbl_addr_set(struct aq_hw_s *aq_hw, u32 rss_redir_tbl_addr)
                            rss_redir_tbl_addr);
 }
 
-void rpf_rss_redir_tbl_wr_data_set(struct aq_hw_s *aq_hw,
-                                  u32 rss_redir_tbl_wr_data)
+void hw_atl_rpf_rss_redir_tbl_wr_data_set(struct aq_hw_s *aq_hw,
+                                         u32 rss_redir_tbl_wr_data)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_WR_DATA_ADR,
                            HW_ATL_RPF_RSS_REDIR_WR_DATA_MSK,
@@ -771,21 +797,22 @@ void rpf_rss_redir_tbl_wr_data_set(struct aq_hw_s *aq_hw,
                            rss_redir_tbl_wr_data);
 }
 
-u32 rpf_rss_redir_wr_en_get(struct aq_hw_s *aq_hw)
+u32 hw_atl_rpf_rss_redir_wr_en_get(struct aq_hw_s *aq_hw)
 {
        return aq_hw_read_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_WR_ENI_ADR,
                                  HW_ATL_RPF_RSS_REDIR_WR_ENI_MSK,
                                  HW_ATL_RPF_RSS_REDIR_WR_ENI_SHIFT);
 }
 
-void rpf_rss_redir_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_redir_wr_en)
+void hw_atl_rpf_rss_redir_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_redir_wr_en)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_WR_ENI_ADR,
                            HW_ATL_RPF_RSS_REDIR_WR_ENI_MSK,
                            HW_ATL_RPF_RSS_REDIR_WR_ENI_SHIFT, rss_redir_wr_en);
 }
 
-void rpf_tpo_to_rpf_sys_lbk_set(struct aq_hw_s *aq_hw, u32 tpo_to_rpf_sys_lbk)
+void hw_atl_rpf_tpo_to_rpf_sys_lbk_set(struct aq_hw_s *aq_hw,
+                                      u32 tpo_to_rpf_sys_lbk)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_TPO_RPF_SYS_LBK_ADR,
                            HW_ATL_RPF_TPO_RPF_SYS_LBK_MSK,
@@ -793,7 +820,7 @@ void rpf_tpo_to_rpf_sys_lbk_set(struct aq_hw_s *aq_hw, u32 tpo_to_rpf_sys_lbk)
                            tpo_to_rpf_sys_lbk);
 }
 
-void rpf_vlan_inner_etht_set(struct aq_hw_s *aq_hw, u32 vlan_inner_etht)
+void hw_atl_rpf_vlan_inner_etht_set(struct aq_hw_s *aq_hw, u32 vlan_inner_etht)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_INNER_TPID_ADR,
                            HW_ATL_RPF_VL_INNER_TPID_MSK,
@@ -801,7 +828,7 @@ void rpf_vlan_inner_etht_set(struct aq_hw_s *aq_hw, u32 vlan_inner_etht)
                            vlan_inner_etht);
 }
 
-void rpf_vlan_outer_etht_set(struct aq_hw_s *aq_hw, u32 vlan_outer_etht)
+void hw_atl_rpf_vlan_outer_etht_set(struct aq_hw_s *aq_hw, u32 vlan_outer_etht)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_OUTER_TPID_ADR,
                            HW_ATL_RPF_VL_OUTER_TPID_MSK,
@@ -809,7 +836,8 @@ void rpf_vlan_outer_etht_set(struct aq_hw_s *aq_hw, u32 vlan_outer_etht)
                            vlan_outer_etht);
 }
 
-void rpf_vlan_prom_mode_en_set(struct aq_hw_s *aq_hw, u32 vlan_prom_mode_en)
+void hw_atl_rpf_vlan_prom_mode_en_set(struct aq_hw_s *aq_hw,
+                                     u32 vlan_prom_mode_en)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_PROMIS_MODE_ADR,
                            HW_ATL_RPF_VL_PROMIS_MODE_MSK,
@@ -817,16 +845,17 @@ void rpf_vlan_prom_mode_en_set(struct aq_hw_s *aq_hw, u32 vlan_prom_mode_en)
                            vlan_prom_mode_en);
 }
 
-void rpf_vlan_accept_untagged_packets_set(struct aq_hw_s *aq_hw,
-                                         u32 vlan_accept_untagged_packets)
+void hw_atl_rpf_vlan_accept_untagged_packets_set(struct aq_hw_s *aq_hw,
+                                                u32 vlan_acc_untagged_packets)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_ADR,
                            HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_MSK,
                            HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_SHIFT,
-                           vlan_accept_untagged_packets);
+                           vlan_acc_untagged_packets);
 }
 
-void rpf_vlan_untagged_act_set(struct aq_hw_s *aq_hw, u32 vlan_untagged_act)
+void hw_atl_rpf_vlan_untagged_act_set(struct aq_hw_s *aq_hw,
+                                     u32 vlan_untagged_act)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_UNTAGGED_ACT_ADR,
                            HW_ATL_RPF_VL_UNTAGGED_ACT_MSK,
@@ -834,7 +863,8 @@ void rpf_vlan_untagged_act_set(struct aq_hw_s *aq_hw, u32 vlan_untagged_act)
                            vlan_untagged_act);
 }
 
-void rpf_vlan_flr_en_set(struct aq_hw_s *aq_hw, u32 vlan_flr_en, u32 filter)
+void hw_atl_rpf_vlan_flr_en_set(struct aq_hw_s *aq_hw, u32 vlan_flr_en,
+                               u32 filter)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_EN_F_ADR(filter),
                            HW_ATL_RPF_VL_EN_F_MSK,
@@ -842,7 +872,8 @@ void rpf_vlan_flr_en_set(struct aq_hw_s *aq_hw, u32 vlan_flr_en, u32 filter)
                            vlan_flr_en);
 }
 
-void rpf_vlan_flr_act_set(struct aq_hw_s *aq_hw, u32 vlan_flr_act, u32 filter)
+void hw_atl_rpf_vlan_flr_act_set(struct aq_hw_s *aq_hw, u32 vlan_flr_act,
+                                u32 filter)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ACT_F_ADR(filter),
                            HW_ATL_RPF_VL_ACT_F_MSK,
@@ -850,7 +881,8 @@ void rpf_vlan_flr_act_set(struct aq_hw_s *aq_hw, u32 vlan_flr_act, u32 filter)
                            vlan_flr_act);
 }
 
-void rpf_vlan_id_flr_set(struct aq_hw_s *aq_hw, u32 vlan_id_flr, u32 filter)
+void hw_atl_rpf_vlan_id_flr_set(struct aq_hw_s *aq_hw, u32 vlan_id_flr,
+                               u32 filter)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ID_F_ADR(filter),
                            HW_ATL_RPF_VL_ID_F_MSK,
@@ -858,23 +890,25 @@ void rpf_vlan_id_flr_set(struct aq_hw_s *aq_hw, u32 vlan_id_flr, u32 filter)
                            vlan_id_flr);
 }
 
-void rpf_etht_flr_en_set(struct aq_hw_s *aq_hw, u32 etht_flr_en, u32 filter)
+void hw_atl_rpf_etht_flr_en_set(struct aq_hw_s *aq_hw, u32 etht_flr_en,
+                               u32 filter)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_ENF_ADR(filter),
                            HW_ATL_RPF_ET_ENF_MSK,
                            HW_ATL_RPF_ET_ENF_SHIFT, etht_flr_en);
 }
 
-void rpf_etht_user_priority_en_set(struct aq_hw_s *aq_hw,
-                                  u32 etht_user_priority_en, u32 filter)
+void hw_atl_rpf_etht_user_priority_en_set(struct aq_hw_s *aq_hw,
+                                         u32 etht_user_priority_en, u32 filter)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_UPFEN_ADR(filter),
                            HW_ATL_RPF_ET_UPFEN_MSK, HW_ATL_RPF_ET_UPFEN_SHIFT,
                            etht_user_priority_en);
 }
 
-void rpf_etht_rx_queue_en_set(struct aq_hw_s *aq_hw, u32 etht_rx_queue_en,
-                             u32 filter)
+void hw_atl_rpf_etht_rx_queue_en_set(struct aq_hw_s *aq_hw,
+                                    u32 etht_rx_queue_en,
+                                    u32 filter)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_RXQFEN_ADR(filter),
                            HW_ATL_RPF_ET_RXQFEN_MSK,
@@ -882,24 +916,25 @@ void rpf_etht_rx_queue_en_set(struct aq_hw_s *aq_hw, u32 etht_rx_queue_en,
                            etht_rx_queue_en);
 }
 
-void rpf_etht_user_priority_set(struct aq_hw_s *aq_hw, u32 etht_user_priority,
-                               u32 filter)
+void hw_atl_rpf_etht_user_priority_set(struct aq_hw_s *aq_hw,
+                                      u32 etht_user_priority,
+                                      u32 filter)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_UPF_ADR(filter),
                            HW_ATL_RPF_ET_UPF_MSK,
                            HW_ATL_RPF_ET_UPF_SHIFT, etht_user_priority);
 }
 
-void rpf_etht_rx_queue_set(struct aq_hw_s *aq_hw, u32 etht_rx_queue,
-                          u32 filter)
+void hw_atl_rpf_etht_rx_queue_set(struct aq_hw_s *aq_hw, u32 etht_rx_queue,
+                                 u32 filter)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_RXQF_ADR(filter),
                            HW_ATL_RPF_ET_RXQF_MSK,
                            HW_ATL_RPF_ET_RXQF_SHIFT, etht_rx_queue);
 }
 
-void rpf_etht_mgt_queue_set(struct aq_hw_s *aq_hw, u32 etht_mgt_queue,
-                           u32 filter)
+void hw_atl_rpf_etht_mgt_queue_set(struct aq_hw_s *aq_hw, u32 etht_mgt_queue,
+                                  u32 filter)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_MNG_RXQF_ADR(filter),
                            HW_ATL_RPF_ET_MNG_RXQF_MSK,
@@ -907,14 +942,15 @@ void rpf_etht_mgt_queue_set(struct aq_hw_s *aq_hw, u32 etht_mgt_queue,
                            etht_mgt_queue);
 }
 
-void rpf_etht_flr_act_set(struct aq_hw_s *aq_hw, u32 etht_flr_act, u32 filter)
+void hw_atl_rpf_etht_flr_act_set(struct aq_hw_s *aq_hw, u32 etht_flr_act,
+                                u32 filter)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_ACTF_ADR(filter),
                            HW_ATL_RPF_ET_ACTF_MSK,
                            HW_ATL_RPF_ET_ACTF_SHIFT, etht_flr_act);
 }
 
-void rpf_etht_flr_set(struct aq_hw_s *aq_hw, u32 etht_flr, u32 filter)
+void hw_atl_rpf_etht_flr_set(struct aq_hw_s *aq_hw, u32 etht_flr, u32 filter)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_VALF_ADR(filter),
                            HW_ATL_RPF_ET_VALF_MSK,
@@ -922,8 +958,8 @@ void rpf_etht_flr_set(struct aq_hw_s *aq_hw, u32 etht_flr, u32 filter)
 }
 
 /* RPO: rx packet offload */
-void rpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw,
-                                      u32 ipv4header_crc_offload_en)
+void hw_atl_rpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw,
+                                             u32 ipv4header_crc_offload_en)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_IPV4CHK_EN_ADR,
                            HW_ATL_RPO_IPV4CHK_EN_MSK,
@@ -931,8 +967,9 @@ void rpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw,
                            ipv4header_crc_offload_en);
 }
 
-void rpo_rx_desc_vlan_stripping_set(struct aq_hw_s *aq_hw,
-                                   u32 rx_desc_vlan_stripping, u32 descriptor)
+void hw_atl_rpo_rx_desc_vlan_stripping_set(struct aq_hw_s *aq_hw,
+                                          u32 rx_desc_vlan_stripping,
+                                          u32 descriptor)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_DESCDVL_STRIP_ADR(descriptor),
                            HW_ATL_RPO_DESCDVL_STRIP_MSK,
@@ -940,21 +977,21 @@ void rpo_rx_desc_vlan_stripping_set(struct aq_hw_s *aq_hw,
                            rx_desc_vlan_stripping);
 }
 
-void rpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw,
-                                   u32 tcp_udp_crc_offload_en)
+void hw_atl_rpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw,
+                                          u32 tcp_udp_crc_offload_en)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPOL4CHK_EN_ADR,
                            HW_ATL_RPOL4CHK_EN_MSK,
                            HW_ATL_RPOL4CHK_EN_SHIFT, tcp_udp_crc_offload_en);
 }
 
-void rpo_lro_en_set(struct aq_hw_s *aq_hw, u32 lro_en)
+void hw_atl_rpo_lro_en_set(struct aq_hw_s *aq_hw, u32 lro_en)
 {
        aq_hw_write_reg(aq_hw, HW_ATL_RPO_LRO_EN_ADR, lro_en);
 }
 
-void rpo_lro_patch_optimization_en_set(struct aq_hw_s *aq_hw,
-                                      u32 lro_patch_optimization_en)
+void hw_atl_rpo_lro_patch_optimization_en_set(struct aq_hw_s *aq_hw,
+                                             u32 lro_patch_optimization_en)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_PTOPT_EN_ADR,
                            HW_ATL_RPO_LRO_PTOPT_EN_MSK,
@@ -962,8 +999,8 @@ void rpo_lro_patch_optimization_en_set(struct aq_hw_s *aq_hw,
                            lro_patch_optimization_en);
 }
 
-void rpo_lro_qsessions_lim_set(struct aq_hw_s *aq_hw,
-                              u32 lro_qsessions_lim)
+void hw_atl_rpo_lro_qsessions_lim_set(struct aq_hw_s *aq_hw,
+                                     u32 lro_qsessions_lim)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_QSES_LMT_ADR,
                            HW_ATL_RPO_LRO_QSES_LMT_MSK,
@@ -971,7 +1008,8 @@ void rpo_lro_qsessions_lim_set(struct aq_hw_s *aq_hw,
                            lro_qsessions_lim);
 }
 
-void rpo_lro_total_desc_lim_set(struct aq_hw_s *aq_hw, u32 lro_total_desc_lim)
+void hw_atl_rpo_lro_total_desc_lim_set(struct aq_hw_s *aq_hw,
+                                      u32 lro_total_desc_lim)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_TOT_DSC_LMT_ADR,
                            HW_ATL_RPO_LRO_TOT_DSC_LMT_MSK,
@@ -979,8 +1017,8 @@ void rpo_lro_total_desc_lim_set(struct aq_hw_s *aq_hw, u32 lro_total_desc_lim)
                            lro_total_desc_lim);
 }
 
-void rpo_lro_min_pay_of_first_pkt_set(struct aq_hw_s *aq_hw,
-                                     u32 lro_min_pld_of_first_pkt)
+void hw_atl_rpo_lro_min_pay_of_first_pkt_set(struct aq_hw_s *aq_hw,
+                                            u32 lro_min_pld_of_first_pkt)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_PKT_MIN_ADR,
                            HW_ATL_RPO_LRO_PKT_MIN_MSK,
@@ -988,14 +1026,14 @@ void rpo_lro_min_pay_of_first_pkt_set(struct aq_hw_s *aq_hw,
                            lro_min_pld_of_first_pkt);
 }
 
-void rpo_lro_pkt_lim_set(struct aq_hw_s *aq_hw, u32 lro_pkt_lim)
+void hw_atl_rpo_lro_pkt_lim_set(struct aq_hw_s *aq_hw, u32 lro_pkt_lim)
 {
        aq_hw_write_reg(aq_hw, HW_ATL_RPO_LRO_RSC_MAX_ADR, lro_pkt_lim);
 }
 
-void rpo_lro_max_num_of_descriptors_set(struct aq_hw_s *aq_hw,
-                                       u32 lro_max_number_of_descriptors,
-                                       u32 lro)
+void hw_atl_rpo_lro_max_num_of_descriptors_set(struct aq_hw_s *aq_hw,
+                                              u32 lro_max_number_of_descriptors,
+                                              u32 lro)
 {
 /* Register address for bitfield lro{L}_des_max[1:0] */
        static u32 rpo_lro_ldes_max_adr[32] = {
@@ -1035,8 +1073,8 @@ void rpo_lro_max_num_of_descriptors_set(struct aq_hw_s *aq_hw,
                            lro_max_number_of_descriptors);
 }
 
-void rpo_lro_time_base_divider_set(struct aq_hw_s *aq_hw,
-                                  u32 lro_time_base_divider)
+void hw_atl_rpo_lro_time_base_divider_set(struct aq_hw_s *aq_hw,
+                                         u32 lro_time_base_divider)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_TB_DIV_ADR,
                            HW_ATL_RPO_LRO_TB_DIV_MSK,
@@ -1044,8 +1082,8 @@ void rpo_lro_time_base_divider_set(struct aq_hw_s *aq_hw,
                            lro_time_base_divider);
 }
 
-void rpo_lro_inactive_interval_set(struct aq_hw_s *aq_hw,
-                                  u32 lro_inactive_interval)
+void hw_atl_rpo_lro_inactive_interval_set(struct aq_hw_s *aq_hw,
+                                         u32 lro_inactive_interval)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_INA_IVAL_ADR,
                            HW_ATL_RPO_LRO_INA_IVAL_MSK,
@@ -1053,17 +1091,17 @@ void rpo_lro_inactive_interval_set(struct aq_hw_s *aq_hw,
                            lro_inactive_interval);
 }
 
-void rpo_lro_max_coalescing_interval_set(struct aq_hw_s *aq_hw,
-                                        u32 lro_max_coalescing_interval)
+void hw_atl_rpo_lro_max_coalescing_interval_set(struct aq_hw_s *aq_hw,
+                                               u32 lro_max_coal_interval)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_MAX_IVAL_ADR,
                            HW_ATL_RPO_LRO_MAX_IVAL_MSK,
                            HW_ATL_RPO_LRO_MAX_IVAL_SHIFT,
-                           lro_max_coalescing_interval);
+                           lro_max_coal_interval);
 }
 
 /* rx */
-void rx_rx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 rx_reg_res_dis)
+void hw_atl_rx_rx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 rx_reg_res_dis)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_RX_REG_RES_DSBL_ADR,
                            HW_ATL_RX_REG_RES_DSBL_MSK,
@@ -1072,33 +1110,34 @@ void rx_rx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 rx_reg_res_dis)
 }
 
 /* tdm */
-void tdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca)
+void hw_atl_tdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCADCPUID_ADR(dca),
                            HW_ATL_TDM_DCADCPUID_MSK,
                            HW_ATL_TDM_DCADCPUID_SHIFT, cpuid);
 }
 
-void tdm_large_send_offload_en_set(struct aq_hw_s *aq_hw,
-                                  u32 large_send_offload_en)
+void hw_atl_tdm_large_send_offload_en_set(struct aq_hw_s *aq_hw,
+                                         u32 large_send_offload_en)
 {
        aq_hw_write_reg(aq_hw, HW_ATL_TDM_LSO_EN_ADR, large_send_offload_en);
 }
 
-void tdm_tx_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_dca_en)
+void hw_atl_tdm_tx_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_dca_en)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCA_EN_ADR, HW_ATL_TDM_DCA_EN_MSK,
                            HW_ATL_TDM_DCA_EN_SHIFT, tx_dca_en);
 }
 
-void tdm_tx_dca_mode_set(struct aq_hw_s *aq_hw, u32 tx_dca_mode)
+void hw_atl_tdm_tx_dca_mode_set(struct aq_hw_s *aq_hw, u32 tx_dca_mode)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCA_MODE_ADR,
                            HW_ATL_TDM_DCA_MODE_MSK,
                            HW_ATL_TDM_DCA_MODE_SHIFT, tx_dca_mode);
 }
 
-void tdm_tx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_dca_en, u32 dca)
+void hw_atl_tdm_tx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_dca_en,
+                                  u32 dca)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCADDESC_EN_ADR(dca),
                            HW_ATL_TDM_DCADDESC_EN_MSK,
@@ -1106,7 +1145,8 @@ void tdm_tx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_dca_en, u32 dca)
                            tx_desc_dca_en);
 }
 
-void tdm_tx_desc_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_en, u32 descriptor)
+void hw_atl_tdm_tx_desc_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_en,
+                              u32 descriptor)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DESCDEN_ADR(descriptor),
                            HW_ATL_TDM_DESCDEN_MSK,
@@ -1114,15 +1154,15 @@ void tdm_tx_desc_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_en, u32 descriptor)
                            tx_desc_en);
 }
 
-u32 tdm_tx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor)
+u32 hw_atl_tdm_tx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor)
 {
        return aq_hw_read_reg_bit(aq_hw, HW_ATL_TDM_DESCDHD_ADR(descriptor),
                                  HW_ATL_TDM_DESCDHD_MSK,
                                  HW_ATL_TDM_DESCDHD_SHIFT);
 }
 
-void tdm_tx_desc_len_set(struct aq_hw_s *aq_hw, u32 tx_desc_len,
-                        u32 descriptor)
+void hw_atl_tdm_tx_desc_len_set(struct aq_hw_s *aq_hw, u32 tx_desc_len,
+                               u32 descriptor)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DESCDLEN_ADR(descriptor),
                            HW_ATL_TDM_DESCDLEN_MSK,
@@ -1130,8 +1170,8 @@ void tdm_tx_desc_len_set(struct aq_hw_s *aq_hw, u32 tx_desc_len,
                            tx_desc_len);
 }
 
-void tdm_tx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw,
-                                 u32 tx_desc_wr_wb_irq_en)
+void hw_atl_tdm_tx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw,
+                                        u32 tx_desc_wr_wb_irq_en)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_INT_DESC_WRB_EN_ADR,
                            HW_ATL_TDM_INT_DESC_WRB_EN_MSK,
@@ -1139,9 +1179,9 @@ void tdm_tx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw,
                            tx_desc_wr_wb_irq_en);
 }
 
-void tdm_tx_desc_wr_wb_threshold_set(struct aq_hw_s *aq_hw,
-                                    u32 tx_desc_wr_wb_threshold,
-                                    u32 descriptor)
+void hw_atl_tdm_tx_desc_wr_wb_threshold_set(struct aq_hw_s *aq_hw,
+                                           u32 tx_desc_wr_wb_threshold,
+                                           u32 descriptor)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DESCDWRB_THRESH_ADR(descriptor),
                            HW_ATL_TDM_DESCDWRB_THRESH_MSK,
@@ -1149,8 +1189,8 @@ void tdm_tx_desc_wr_wb_threshold_set(struct aq_hw_s *aq_hw,
                            tx_desc_wr_wb_threshold);
 }
 
-void tdm_tdm_intr_moder_en_set(struct aq_hw_s *aq_hw,
-                              u32 tdm_irq_moderation_en)
+void hw_atl_tdm_tdm_intr_moder_en_set(struct aq_hw_s *aq_hw,
+                                     u32 tdm_irq_moderation_en)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_INT_MOD_EN_ADR,
                            HW_ATL_TDM_INT_MOD_EN_MSK,
@@ -1159,8 +1199,8 @@ void tdm_tdm_intr_moder_en_set(struct aq_hw_s *aq_hw,
 }
 
 /* thm */
-void thm_lso_tcp_flag_of_first_pkt_set(struct aq_hw_s *aq_hw,
-                                      u32 lso_tcp_flag_of_first_pkt)
+void hw_atl_thm_lso_tcp_flag_of_first_pkt_set(struct aq_hw_s *aq_hw,
+                                             u32 lso_tcp_flag_of_first_pkt)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_THM_LSO_TCP_FLAG_FIRST_ADR,
                            HW_ATL_THM_LSO_TCP_FLAG_FIRST_MSK,
@@ -1168,8 +1208,8 @@ void thm_lso_tcp_flag_of_first_pkt_set(struct aq_hw_s *aq_hw,
                            lso_tcp_flag_of_first_pkt);
 }
 
-void thm_lso_tcp_flag_of_last_pkt_set(struct aq_hw_s *aq_hw,
-                                     u32 lso_tcp_flag_of_last_pkt)
+void hw_atl_thm_lso_tcp_flag_of_last_pkt_set(struct aq_hw_s *aq_hw,
+                                            u32 lso_tcp_flag_of_last_pkt)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_THM_LSO_TCP_FLAG_LAST_ADR,
                            HW_ATL_THM_LSO_TCP_FLAG_LAST_MSK,
@@ -1177,8 +1217,8 @@ void thm_lso_tcp_flag_of_last_pkt_set(struct aq_hw_s *aq_hw,
                            lso_tcp_flag_of_last_pkt);
 }
 
-void thm_lso_tcp_flag_of_middle_pkt_set(struct aq_hw_s *aq_hw,
-                                       u32 lso_tcp_flag_of_middle_pkt)
+void hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(struct aq_hw_s *aq_hw,
+                                              u32 lso_tcp_flag_of_middle_pkt)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_THM_LSO_TCP_FLAG_MID_ADR,
                            HW_ATL_THM_LSO_TCP_FLAG_MID_MSK,
@@ -1187,15 +1227,15 @@ void thm_lso_tcp_flag_of_middle_pkt_set(struct aq_hw_s *aq_hw,
 }
 
 /* TPB: tx packet buffer */
-void tpb_tx_buff_en_set(struct aq_hw_s *aq_hw, u32 tx_buff_en)
+void hw_atl_tpb_tx_buff_en_set(struct aq_hw_s *aq_hw, u32 tx_buff_en)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TX_BUF_EN_ADR,
                            HW_ATL_TPB_TX_BUF_EN_MSK,
                            HW_ATL_TPB_TX_BUF_EN_SHIFT, tx_buff_en);
 }
 
-void tpb_tx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw,
-                                        u32 tx_buff_hi_threshold_per_tc,
+void hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw,
+                                               u32 tx_buff_hi_threshold_per_tc,
                                         u32 buffer)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TXBHI_THRESH_ADR(buffer),
@@ -1204,8 +1244,8 @@ void tpb_tx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw,
                            tx_buff_hi_threshold_per_tc);
 }
 
-void tpb_tx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw,
-                                        u32 tx_buff_lo_threshold_per_tc,
+void hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw,
+                                               u32 tx_buff_lo_threshold_per_tc,
                                         u32 buffer)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TXBLO_THRESH_ADR(buffer),
@@ -1214,7 +1254,7 @@ void tpb_tx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw,
                            tx_buff_lo_threshold_per_tc);
 }
 
-void tpb_tx_dma_sys_lbk_en_set(struct aq_hw_s *aq_hw, u32 tx_dma_sys_lbk_en)
+void hw_atl_tpb_tx_dma_sys_lbk_en_set(struct aq_hw_s *aq_hw, u32 tx_dma_sys_lbk_en)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_DMA_SYS_LBK_ADR,
                            HW_ATL_TPB_DMA_SYS_LBK_MSK,
@@ -1222,8 +1262,8 @@ void tpb_tx_dma_sys_lbk_en_set(struct aq_hw_s *aq_hw, u32 tx_dma_sys_lbk_en)
                            tx_dma_sys_lbk_en);
 }
 
-void tpb_tx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
-                                    u32 tx_pkt_buff_size_per_tc, u32 buffer)
+void hw_atl_tpb_tx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
+                                           u32 tx_pkt_buff_size_per_tc, u32 buffer)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TXBBUF_SIZE_ADR(buffer),
                            HW_ATL_TPB_TXBBUF_SIZE_MSK,
@@ -1231,7 +1271,7 @@ void tpb_tx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
                            tx_pkt_buff_size_per_tc);
 }
 
-void tpb_tx_path_scp_ins_en_set(struct aq_hw_s *aq_hw, u32 tx_path_scp_ins_en)
+void hw_atl_tpb_tx_path_scp_ins_en_set(struct aq_hw_s *aq_hw, u32 tx_path_scp_ins_en)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TX_SCP_INS_EN_ADR,
                            HW_ATL_TPB_TX_SCP_INS_EN_MSK,
@@ -1240,8 +1280,8 @@ void tpb_tx_path_scp_ins_en_set(struct aq_hw_s *aq_hw, u32 tx_path_scp_ins_en)
 }
 
 /* TPO: tx packet offload */
-void tpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw,
-                                      u32 ipv4header_crc_offload_en)
+void hw_atl_tpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw,
+                                             u32 ipv4header_crc_offload_en)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_TPO_IPV4CHK_EN_ADR,
                            HW_ATL_TPO_IPV4CHK_EN_MSK,
@@ -1249,8 +1289,8 @@ void tpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw,
                            ipv4header_crc_offload_en);
 }
 
-void tpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw,
-                                   u32 tcp_udp_crc_offload_en)
+void hw_atl_tpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw,
+                                          u32 tcp_udp_crc_offload_en)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_TPOL4CHK_EN_ADR,
                            HW_ATL_TPOL4CHK_EN_MSK,
@@ -1258,7 +1298,8 @@ void tpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw,
                            tcp_udp_crc_offload_en);
 }
 
-void tpo_tx_pkt_sys_lbk_en_set(struct aq_hw_s *aq_hw, u32 tx_pkt_sys_lbk_en)
+void hw_atl_tpo_tx_pkt_sys_lbk_en_set(struct aq_hw_s *aq_hw,
+                                     u32 tx_pkt_sys_lbk_en)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_TPO_PKT_SYS_LBK_ADR,
                            HW_ATL_TPO_PKT_SYS_LBK_MSK,
@@ -1267,8 +1308,8 @@ void tpo_tx_pkt_sys_lbk_en_set(struct aq_hw_s *aq_hw, u32 tx_pkt_sys_lbk_en)
 }
 
 /* TPS: tx packet scheduler */
-void tps_tx_pkt_shed_data_arb_mode_set(struct aq_hw_s *aq_hw,
-                                      u32 tx_pkt_shed_data_arb_mode)
+void hw_atl_tps_tx_pkt_shed_data_arb_mode_set(struct aq_hw_s *aq_hw,
+                                             u32 tx_pkt_shed_data_arb_mode)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DATA_TC_ARB_MODE_ADR,
                            HW_ATL_TPS_DATA_TC_ARB_MODE_MSK,
@@ -1276,8 +1317,8 @@ void tps_tx_pkt_shed_data_arb_mode_set(struct aq_hw_s *aq_hw,
                            tx_pkt_shed_data_arb_mode);
 }
 
-void tps_tx_pkt_shed_desc_rate_curr_time_res_set(struct aq_hw_s *aq_hw,
-                                                u32 curr_time_res)
+void hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(struct aq_hw_s *aq_hw,
+                                                       u32 curr_time_res)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_RATE_TA_RST_ADR,
                            HW_ATL_TPS_DESC_RATE_TA_RST_MSK,
@@ -1285,8 +1326,8 @@ void tps_tx_pkt_shed_desc_rate_curr_time_res_set(struct aq_hw_s *aq_hw,
                            curr_time_res);
 }
 
-void tps_tx_pkt_shed_desc_rate_lim_set(struct aq_hw_s *aq_hw,
-                                      u32 tx_pkt_shed_desc_rate_lim)
+void hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(struct aq_hw_s *aq_hw,
+                                             u32 tx_pkt_shed_desc_rate_lim)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_RATE_LIM_ADR,
                            HW_ATL_TPS_DESC_RATE_LIM_MSK,
@@ -1294,27 +1335,28 @@ void tps_tx_pkt_shed_desc_rate_lim_set(struct aq_hw_s *aq_hw,
                            tx_pkt_shed_desc_rate_lim);
 }
 
-void tps_tx_pkt_shed_desc_tc_arb_mode_set(struct aq_hw_s *aq_hw,
-                                         u32 tx_pkt_shed_desc_tc_arb_mode)
+void hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(struct aq_hw_s *aq_hw,
+                                                u32 arb_mode)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_TC_ARB_MODE_ADR,
                            HW_ATL_TPS_DESC_TC_ARB_MODE_MSK,
                            HW_ATL_TPS_DESC_TC_ARB_MODE_SHIFT,
-                           tx_pkt_shed_desc_tc_arb_mode);
+                           arb_mode);
 }
 
-void tps_tx_pkt_shed_desc_tc_max_credit_set(struct aq_hw_s *aq_hw,
-                                           u32 tx_pkt_shed_desc_tc_max_credit,
-                                           u32 tc)
+void hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(struct aq_hw_s *aq_hw,
+                                                  u32 max_credit,
+                                                  u32 tc)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_TCTCREDIT_MAX_ADR(tc),
                            HW_ATL_TPS_DESC_TCTCREDIT_MAX_MSK,
                            HW_ATL_TPS_DESC_TCTCREDIT_MAX_SHIFT,
-                           tx_pkt_shed_desc_tc_max_credit);
+                           max_credit);
 }
 
-void tps_tx_pkt_shed_desc_tc_weight_set(struct aq_hw_s *aq_hw,
-                                       u32 tx_pkt_shed_desc_tc_weight, u32 tc)
+void hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(struct aq_hw_s *aq_hw,
+                                              u32 tx_pkt_shed_desc_tc_weight,
+                                              u32 tc)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_TCTWEIGHT_ADR(tc),
                            HW_ATL_TPS_DESC_TCTWEIGHT_MSK,
@@ -1322,27 +1364,28 @@ void tps_tx_pkt_shed_desc_tc_weight_set(struct aq_hw_s *aq_hw,
                            tx_pkt_shed_desc_tc_weight);
 }
 
-void tps_tx_pkt_shed_desc_vm_arb_mode_set(struct aq_hw_s *aq_hw,
-                                         u32 tx_pkt_shed_desc_vm_arb_mode)
+void hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(struct aq_hw_s *aq_hw,
+                                                u32 arb_mode)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_VM_ARB_MODE_ADR,
                            HW_ATL_TPS_DESC_VM_ARB_MODE_MSK,
                            HW_ATL_TPS_DESC_VM_ARB_MODE_SHIFT,
-                           tx_pkt_shed_desc_vm_arb_mode);
+                           arb_mode);
 }
 
-void tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw_s *aq_hw,
-                                           u32 tx_pkt_shed_tc_data_max_credit,
-                                           u32 tc)
+void hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw_s *aq_hw,
+                                                  u32 max_credit,
+                                                  u32 tc)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DATA_TCTCREDIT_MAX_ADR(tc),
                            HW_ATL_TPS_DATA_TCTCREDIT_MAX_MSK,
                            HW_ATL_TPS_DATA_TCTCREDIT_MAX_SHIFT,
-                           tx_pkt_shed_tc_data_max_credit);
+                           max_credit);
 }
 
-void tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw_s *aq_hw,
-                                       u32 tx_pkt_shed_tc_data_weight, u32 tc)
+void hw_atl_tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw_s *aq_hw,
+                                              u32 tx_pkt_shed_tc_data_weight,
+                                              u32 tc)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DATA_TCTWEIGHT_ADR(tc),
                            HW_ATL_TPS_DATA_TCTWEIGHT_MSK,
@@ -1351,7 +1394,7 @@ void tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw_s *aq_hw,
 }
 
 /* tx */
-void tx_tx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 tx_reg_res_dis)
+void hw_atl_tx_tx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 tx_reg_res_dis)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_TX_REG_RES_DSBL_ADR,
                            HW_ATL_TX_REG_RES_DSBL_MSK,
@@ -1359,15 +1402,15 @@ void tx_tx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 tx_reg_res_dis)
 }
 
 /* msm */
-u32 msm_reg_access_status_get(struct aq_hw_s *aq_hw)
+u32 hw_atl_msm_reg_access_status_get(struct aq_hw_s *aq_hw)
 {
        return aq_hw_read_reg_bit(aq_hw, HW_ATL_MSM_REG_ACCESS_BUSY_ADR,
                                  HW_ATL_MSM_REG_ACCESS_BUSY_MSK,
                                  HW_ATL_MSM_REG_ACCESS_BUSY_SHIFT);
 }
 
-void msm_reg_addr_for_indirect_addr_set(struct aq_hw_s *aq_hw,
-                                       u32 reg_addr_for_indirect_addr)
+void hw_atl_msm_reg_addr_for_indirect_addr_set(struct aq_hw_s *aq_hw,
+                                              u32 reg_addr_for_indirect_addr)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_MSM_REG_ADDR_ADR,
                            HW_ATL_MSM_REG_ADDR_MSK,
@@ -1375,7 +1418,7 @@ void msm_reg_addr_for_indirect_addr_set(struct aq_hw_s *aq_hw,
                            reg_addr_for_indirect_addr);
 }
 
-void msm_reg_rd_strobe_set(struct aq_hw_s *aq_hw, u32 reg_rd_strobe)
+void hw_atl_msm_reg_rd_strobe_set(struct aq_hw_s *aq_hw, u32 reg_rd_strobe)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_MSM_REG_RD_STROBE_ADR,
                            HW_ATL_MSM_REG_RD_STROBE_MSK,
@@ -1383,17 +1426,17 @@ void msm_reg_rd_strobe_set(struct aq_hw_s *aq_hw, u32 reg_rd_strobe)
                            reg_rd_strobe);
 }
 
-u32 msm_reg_rd_data_get(struct aq_hw_s *aq_hw)
+u32 hw_atl_msm_reg_rd_data_get(struct aq_hw_s *aq_hw)
 {
        return aq_hw_read_reg(aq_hw, HW_ATL_MSM_REG_RD_DATA_ADR);
 }
 
-void msm_reg_wr_data_set(struct aq_hw_s *aq_hw, u32 reg_wr_data)
+void hw_atl_msm_reg_wr_data_set(struct aq_hw_s *aq_hw, u32 reg_wr_data)
 {
        aq_hw_write_reg(aq_hw, HW_ATL_MSM_REG_WR_DATA_ADR, reg_wr_data);
 }
 
-void msm_reg_wr_strobe_set(struct aq_hw_s *aq_hw, u32 reg_wr_strobe)
+void hw_atl_msm_reg_wr_strobe_set(struct aq_hw_s *aq_hw, u32 reg_wr_strobe)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_MSM_REG_WR_STROBE_ADR,
                            HW_ATL_MSM_REG_WR_STROBE_MSK,
@@ -1402,7 +1445,7 @@ void msm_reg_wr_strobe_set(struct aq_hw_s *aq_hw, u32 reg_wr_strobe)
 }
 
 /* pci */
-void pci_pci_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 pci_reg_res_dis)
+void hw_atl_pci_pci_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 pci_reg_res_dis)
 {
        aq_hw_write_reg_bit(aq_hw, HW_ATL_PCI_REG_RES_DSBL_ADR,
                            HW_ATL_PCI_REG_RES_DSBL_MSK,
@@ -1410,8 +1453,9 @@ void pci_pci_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 pci_reg_res_dis)
                            pci_reg_res_dis);
 }
 
-void reg_glb_cpu_scratch_scp_set(struct aq_hw_s *aq_hw, u32 glb_cpu_scratch_scp,
-                                u32 scratch_scp)
+void hw_atl_reg_glb_cpu_scratch_scp_set(struct aq_hw_s *aq_hw,
+                                       u32 glb_cpu_scratch_scp,
+                                       u32 scratch_scp)
 {
        aq_hw_write_reg(aq_hw, HW_ATL_GLB_CPU_SCRATCH_SCP_ADR(scratch_scp),
                        glb_cpu_scratch_scp);
index ed1085b95adb353940f6ab45ee94b30dd5c1c72c..dfb426f2dc2c8ef1aad6971fbd627a2312cf927d 100644 (file)
@@ -21,657 +21,681 @@ struct aq_hw_s;
 /* global */
 
 /* set global microprocessor semaphore */
-void reg_glb_cpu_sem_set(struct aq_hw_s *aq_hw,        u32 glb_cpu_sem,
-                        u32 semaphore);
+void hw_atl_reg_glb_cpu_sem_set(struct aq_hw_s *aq_hw, u32 glb_cpu_sem,
+                               u32 semaphore);
 
 /* get global microprocessor semaphore */
-u32 reg_glb_cpu_sem_get(struct aq_hw_s *aq_hw, u32 semaphore);
+u32 hw_atl_reg_glb_cpu_sem_get(struct aq_hw_s *aq_hw, u32 semaphore);
 
 /* set global register reset disable */
-void glb_glb_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 glb_reg_res_dis);
+void hw_atl_glb_glb_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 glb_reg_res_dis);
 
 /* set soft reset */
-void glb_soft_res_set(struct aq_hw_s *aq_hw, u32 soft_res);
+void hw_atl_glb_soft_res_set(struct aq_hw_s *aq_hw, u32 soft_res);
 
 /* get soft reset */
-u32 glb_soft_res_get(struct aq_hw_s *aq_hw);
+u32 hw_atl_glb_soft_res_get(struct aq_hw_s *aq_hw);
 
 /* stats */
 
-u32 rpb_rx_dma_drop_pkt_cnt_get(struct aq_hw_s *aq_hw);
+u32 hw_atl_rpb_rx_dma_drop_pkt_cnt_get(struct aq_hw_s *aq_hw);
 
 /* get rx dma good octet counter lsw */
-u32 stats_rx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw);
+u32 hw_atl_stats_rx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw);
 
 /* get rx dma good packet counter lsw */
-u32 stats_rx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw);
+u32 hw_atl_stats_rx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw);
 
 /* get tx dma good octet counter lsw */
-u32 stats_tx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw);
+u32 hw_atl_stats_tx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw);
 
 /* get tx dma good packet counter lsw */
-u32 stats_tx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw);
+u32 hw_atl_stats_tx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw);
 
 /* get rx dma good octet counter msw */
-u32 stats_rx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw);
+u32 hw_atl_stats_rx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw);
 
 /* get rx dma good packet counter msw */
-u32 stats_rx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw);
+u32 hw_atl_stats_rx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw);
 
 /* get tx dma good octet counter msw */
-u32 stats_tx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw);
+u32 hw_atl_stats_tx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw);
 
 /* get tx dma good packet counter msw */
-u32 stats_tx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw);
+u32 hw_atl_stats_tx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw);
 
 /* get msm rx errors counter register */
-u32 reg_mac_msm_rx_errs_cnt_get(struct aq_hw_s *aq_hw);
+u32 hw_atl_reg_mac_msm_rx_errs_cnt_get(struct aq_hw_s *aq_hw);
 
 /* get msm rx unicast frames counter register */
-u32 reg_mac_msm_rx_ucst_frm_cnt_get(struct aq_hw_s *aq_hw);
+u32 hw_atl_reg_mac_msm_rx_ucst_frm_cnt_get(struct aq_hw_s *aq_hw);
 
 /* get msm rx multicast frames counter register */
-u32 reg_mac_msm_rx_mcst_frm_cnt_get(struct aq_hw_s *aq_hw);
+u32 hw_atl_reg_mac_msm_rx_mcst_frm_cnt_get(struct aq_hw_s *aq_hw);
 
 /* get msm rx broadcast frames counter register */
-u32 reg_mac_msm_rx_bcst_frm_cnt_get(struct aq_hw_s *aq_hw);
+u32 hw_atl_reg_mac_msm_rx_bcst_frm_cnt_get(struct aq_hw_s *aq_hw);
 
 /* get msm rx broadcast octets counter register 1 */
-u32 reg_mac_msm_rx_bcst_octets_counter1get(struct aq_hw_s *aq_hw);
+u32 hw_atl_reg_mac_msm_rx_bcst_octets_counter1get(struct aq_hw_s *aq_hw);
 
 /* get msm rx unicast octets counter register 0 */
-u32 reg_mac_msm_rx_ucst_octets_counter0get(struct aq_hw_s *aq_hw);
+u32 hw_atl_reg_mac_msm_rx_ucst_octets_counter0get(struct aq_hw_s *aq_hw);
 
 /* get rx dma statistics counter 7 */
-u32 reg_rx_dma_stat_counter7get(struct aq_hw_s *aq_hw);
+u32 hw_atl_reg_rx_dma_stat_counter7get(struct aq_hw_s *aq_hw);
 
 /* get msm tx errors counter register */
-u32 reg_mac_msm_tx_errs_cnt_get(struct aq_hw_s *aq_hw);
+u32 hw_atl_reg_mac_msm_tx_errs_cnt_get(struct aq_hw_s *aq_hw);
 
 /* get msm tx unicast frames counter register */
-u32 reg_mac_msm_tx_ucst_frm_cnt_get(struct aq_hw_s *aq_hw);
+u32 hw_atl_reg_mac_msm_tx_ucst_frm_cnt_get(struct aq_hw_s *aq_hw);
 
 /* get msm tx multicast frames counter register */
-u32 reg_mac_msm_tx_mcst_frm_cnt_get(struct aq_hw_s *aq_hw);
+u32 hw_atl_reg_mac_msm_tx_mcst_frm_cnt_get(struct aq_hw_s *aq_hw);
 
 /* get msm tx broadcast frames counter register */
-u32 reg_mac_msm_tx_bcst_frm_cnt_get(struct aq_hw_s *aq_hw);
+u32 hw_atl_reg_mac_msm_tx_bcst_frm_cnt_get(struct aq_hw_s *aq_hw);
 
 /* get msm tx multicast octets counter register 1 */
-u32 reg_mac_msm_tx_mcst_octets_counter1get(struct aq_hw_s *aq_hw);
+u32 hw_atl_reg_mac_msm_tx_mcst_octets_counter1get(struct aq_hw_s *aq_hw);
 
 /* get msm tx broadcast octets counter register 1 */
-u32 reg_mac_msm_tx_bcst_octets_counter1get(struct aq_hw_s *aq_hw);
+u32 hw_atl_reg_mac_msm_tx_bcst_octets_counter1get(struct aq_hw_s *aq_hw);
 
 /* get msm tx unicast octets counter register 0 */
-u32 reg_mac_msm_tx_ucst_octets_counter0get(struct aq_hw_s *aq_hw);
+u32 hw_atl_reg_mac_msm_tx_ucst_octets_counter0get(struct aq_hw_s *aq_hw);
 
 /* get global mif identification */
-u32 reg_glb_mif_id_get(struct aq_hw_s *aq_hw);
+u32 hw_atl_reg_glb_mif_id_get(struct aq_hw_s *aq_hw);
 
 /* interrupt */
 
 /* set interrupt auto mask lsw */
-void itr_irq_auto_masklsw_set(struct aq_hw_s *aq_hw, u32 irq_auto_masklsw);
+void hw_atl_itr_irq_auto_masklsw_set(struct aq_hw_s *aq_hw,
+                                    u32 irq_auto_masklsw);
 
 /* set interrupt mapping enable rx */
-void itr_irq_map_en_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_rx, u32 rx);
+void hw_atl_itr_irq_map_en_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_rx,
+                                 u32 rx);
 
 /* set interrupt mapping enable tx */
-void itr_irq_map_en_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_tx, u32 tx);
+void hw_atl_itr_irq_map_en_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_tx,
+                                 u32 tx);
 
 /* set interrupt mapping rx */
-void itr_irq_map_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_rx, u32 rx);
+void hw_atl_itr_irq_map_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_rx, u32 rx);
 
 /* set interrupt mapping tx */
-void itr_irq_map_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_tx, u32 tx);
+void hw_atl_itr_irq_map_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_tx, u32 tx);
 
 /* set interrupt mask clear lsw */
-void itr_irq_msk_clearlsw_set(struct aq_hw_s *aq_hw, u32 irq_msk_clearlsw);
+void hw_atl_itr_irq_msk_clearlsw_set(struct aq_hw_s *aq_hw,
+                                    u32 irq_msk_clearlsw);
 
 /* set interrupt mask set lsw */
-void itr_irq_msk_setlsw_set(struct aq_hw_s *aq_hw, u32 irq_msk_setlsw);
+void hw_atl_itr_irq_msk_setlsw_set(struct aq_hw_s *aq_hw, u32 irq_msk_setlsw);
 
 /* set interrupt register reset disable */
-void itr_irq_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 irq_reg_res_dis);
+void hw_atl_itr_irq_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 irq_reg_res_dis);
 
 /* set interrupt status clear lsw */
-void itr_irq_status_clearlsw_set(struct aq_hw_s *aq_hw,
-                                u32 irq_status_clearlsw);
+void hw_atl_itr_irq_status_clearlsw_set(struct aq_hw_s *aq_hw,
+                                       u32 irq_status_clearlsw);
 
 /* get interrupt status lsw */
-u32 itr_irq_statuslsw_get(struct aq_hw_s *aq_hw);
+u32 hw_atl_itr_irq_statuslsw_get(struct aq_hw_s *aq_hw);
 
 /* get reset interrupt */
-u32 itr_res_irq_get(struct aq_hw_s *aq_hw);
+u32 hw_atl_itr_res_irq_get(struct aq_hw_s *aq_hw);
 
 /* set reset interrupt */
-void itr_res_irq_set(struct aq_hw_s *aq_hw, u32 res_irq);
+void hw_atl_itr_res_irq_set(struct aq_hw_s *aq_hw, u32 res_irq);
 
 /* rdm */
 
 /* set cpu id */
-void rdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca);
+void hw_atl_rdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca);
 
 /* set rx dca enable */
-void rdm_rx_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_dca_en);
+void hw_atl_rdm_rx_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_dca_en);
 
 /* set rx dca mode */
-void rdm_rx_dca_mode_set(struct aq_hw_s *aq_hw, u32 rx_dca_mode);
+void hw_atl_rdm_rx_dca_mode_set(struct aq_hw_s *aq_hw, u32 rx_dca_mode);
 
 /* set rx descriptor data buffer size */
-void rdm_rx_desc_data_buff_size_set(struct aq_hw_s *aq_hw,
-                                   u32 rx_desc_data_buff_size,
+void hw_atl_rdm_rx_desc_data_buff_size_set(struct aq_hw_s *aq_hw,
+                                          u32 rx_desc_data_buff_size,
                                    u32 descriptor);
 
 /* set rx descriptor dca enable */
-void rdm_rx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_dca_en,
-                           u32 dca);
+void hw_atl_rdm_rx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_dca_en,
+                                  u32 dca);
 
 /* set rx descriptor enable */
-void rdm_rx_desc_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_en,
-                       u32 descriptor);
+void hw_atl_rdm_rx_desc_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_en,
+                              u32 descriptor);
 
 /* set rx descriptor header splitting */
-void rdm_rx_desc_head_splitting_set(struct aq_hw_s *aq_hw,
-                                   u32 rx_desc_head_splitting,
+void hw_atl_rdm_rx_desc_head_splitting_set(struct aq_hw_s *aq_hw,
+                                          u32 rx_desc_head_splitting,
                                    u32 descriptor);
 
 /* get rx descriptor head pointer */
-u32 rdm_rx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor);
+u32 hw_atl_rdm_rx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor);
 
 /* set rx descriptor length */
-void rdm_rx_desc_len_set(struct aq_hw_s *aq_hw, u32 rx_desc_len,
-                        u32 descriptor);
+void hw_atl_rdm_rx_desc_len_set(struct aq_hw_s *aq_hw, u32 rx_desc_len,
+                               u32 descriptor);
 
 /* set rx descriptor write-back interrupt enable */
-void rdm_rx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw,
-                                 u32 rx_desc_wr_wb_irq_en);
+void hw_atl_rdm_rx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw,
+                                        u32 rx_desc_wr_wb_irq_en);
 
 /* set rx header dca enable */
-void rdm_rx_head_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_head_dca_en,
-                           u32 dca);
+void hw_atl_rdm_rx_head_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_head_dca_en,
+                                  u32 dca);
 
 /* set rx payload dca enable */
-void rdm_rx_pld_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_pld_dca_en, u32 dca);
+void hw_atl_rdm_rx_pld_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_pld_dca_en,
+                                 u32 dca);
 
 /* set rx descriptor header buffer size */
-void rdm_rx_desc_head_buff_size_set(struct aq_hw_s *aq_hw,
-                                   u32 rx_desc_head_buff_size,
-                                   u32 descriptor);
+void hw_atl_rdm_rx_desc_head_buff_size_set(struct aq_hw_s *aq_hw,
+                                          u32 rx_desc_head_buff_size,
+                                          u32 descriptor);
 
 /* set rx descriptor reset */
-void rdm_rx_desc_res_set(struct aq_hw_s *aq_hw, u32 rx_desc_res,
-                        u32 descriptor);
+void hw_atl_rdm_rx_desc_res_set(struct aq_hw_s *aq_hw, u32 rx_desc_res,
+                               u32 descriptor);
 
 /* Set RDM Interrupt Moderation Enable */
-void rdm_rdm_intr_moder_en_set(struct aq_hw_s *aq_hw, u32 rdm_intr_moder_en);
+void hw_atl_rdm_rdm_intr_moder_en_set(struct aq_hw_s *aq_hw,
+                                     u32 rdm_intr_moder_en);
 
 /* reg */
 
 /* set general interrupt mapping register */
-void reg_gen_irq_map_set(struct aq_hw_s *aq_hw, u32 gen_intr_map, u32 regidx);
+void hw_atl_reg_gen_irq_map_set(struct aq_hw_s *aq_hw, u32 gen_intr_map,
+                               u32 regidx);
 
 /* get general interrupt status register */
-u32 reg_gen_irq_status_get(struct aq_hw_s *aq_hw);
+u32 hw_atl_reg_gen_irq_status_get(struct aq_hw_s *aq_hw);
 
 /* set interrupt global control register */
-void reg_irq_glb_ctl_set(struct aq_hw_s *aq_hw, u32 intr_glb_ctl);
+void hw_atl_reg_irq_glb_ctl_set(struct aq_hw_s *aq_hw, u32 intr_glb_ctl);
 
 /* set interrupt throttle register */
-void reg_irq_thr_set(struct aq_hw_s *aq_hw, u32 intr_thr, u32 throttle);
+void hw_atl_reg_irq_thr_set(struct aq_hw_s *aq_hw, u32 intr_thr, u32 throttle);
 
 /* set rx dma descriptor base address lsw */
-void reg_rx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw,
-                                       u32 rx_dma_desc_base_addrlsw,
+void hw_atl_reg_rx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw,
+                                              u32 rx_dma_desc_base_addrlsw,
                                        u32 descriptor);
 
 /* set rx dma descriptor base address msw */
-void reg_rx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw,
-                                       u32 rx_dma_desc_base_addrmsw,
+void hw_atl_reg_rx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw,
+                                              u32 rx_dma_desc_base_addrmsw,
                                        u32 descriptor);
 
 /* get rx dma descriptor status register */
-u32 reg_rx_dma_desc_status_get(struct aq_hw_s *aq_hw, u32 descriptor);
+u32 hw_atl_reg_rx_dma_desc_status_get(struct aq_hw_s *aq_hw, u32 descriptor);
 
 /* set rx dma descriptor tail pointer register */
-void reg_rx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw,
-                                 u32 rx_dma_desc_tail_ptr,
+void hw_atl_reg_rx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw,
+                                        u32 rx_dma_desc_tail_ptr,
                                  u32 descriptor);
 
 /* set rx filter multicast filter mask register */
-void reg_rx_flr_mcst_flr_msk_set(struct aq_hw_s *aq_hw,
-                                u32 rx_flr_mcst_flr_msk);
+void hw_atl_reg_rx_flr_mcst_flr_msk_set(struct aq_hw_s *aq_hw,
+                                       u32 rx_flr_mcst_flr_msk);
 
 /* set rx filter multicast filter register */
-void reg_rx_flr_mcst_flr_set(struct aq_hw_s *aq_hw, u32 rx_flr_mcst_flr,
-                            u32 filter);
+void hw_atl_reg_rx_flr_mcst_flr_set(struct aq_hw_s *aq_hw, u32 rx_flr_mcst_flr,
+                                   u32 filter);
 
 /* set rx filter rss control register 1 */
-void reg_rx_flr_rss_control1set(struct aq_hw_s *aq_hw,
-                               u32 rx_flr_rss_control1);
+void hw_atl_reg_rx_flr_rss_control1set(struct aq_hw_s *aq_hw,
+                                      u32 rx_flr_rss_control1);
 
 /* Set RX Filter Control Register 2 */
-void reg_rx_flr_control2_set(struct aq_hw_s *aq_hw, u32 rx_flr_control2);
+void hw_atl_reg_rx_flr_control2_set(struct aq_hw_s *aq_hw, u32 rx_flr_control2);
 
 /* Set RX Interrupt Moderation Control Register */
-void reg_rx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw,
-                               u32 rx_intr_moderation_ctl,
+void hw_atl_reg_rx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw,
+                                      u32 rx_intr_moderation_ctl,
                                u32 queue);
 
 /* set tx dma debug control */
-void reg_tx_dma_debug_ctl_set(struct aq_hw_s *aq_hw, u32 tx_dma_debug_ctl);
+void hw_atl_reg_tx_dma_debug_ctl_set(struct aq_hw_s *aq_hw,
+                                    u32 tx_dma_debug_ctl);
 
 /* set tx dma descriptor base address lsw */
-void reg_tx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw,
-                                       u32 tx_dma_desc_base_addrlsw,
+void hw_atl_reg_tx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw,
+                                              u32 tx_dma_desc_base_addrlsw,
                                        u32 descriptor);
 
 /* set tx dma descriptor base address msw */
-void reg_tx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw,
-                                       u32 tx_dma_desc_base_addrmsw,
+void hw_atl_reg_tx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw,
+                                              u32 tx_dma_desc_base_addrmsw,
                                        u32 descriptor);
 
 /* set tx dma descriptor tail pointer register */
-void reg_tx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw,
-                                 u32 tx_dma_desc_tail_ptr,
-                                 u32 descriptor);
+void hw_atl_reg_tx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw,
+                                        u32 tx_dma_desc_tail_ptr,
+                                        u32 descriptor);
 
 /* Set TX Interrupt Moderation Control Register */
-void reg_tx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw,
-                               u32 tx_intr_moderation_ctl,
-                               u32 queue);
+void hw_atl_reg_tx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw,
+                                      u32 tx_intr_moderation_ctl,
+                                      u32 queue);
 
 /* set global microprocessor scratch pad */
-void reg_glb_cpu_scratch_scp_set(struct aq_hw_s *aq_hw,
-                                u32 glb_cpu_scratch_scp, u32 scratch_scp);
+void hw_atl_reg_glb_cpu_scratch_scp_set(struct aq_hw_s *aq_hw,
+                                       u32 glb_cpu_scratch_scp,
+                                       u32 scratch_scp);
 
 /* rpb */
 
 /* set dma system loopback */
-void rpb_dma_sys_lbk_set(struct aq_hw_s *aq_hw, u32 dma_sys_lbk);
+void hw_atl_rpb_dma_sys_lbk_set(struct aq_hw_s *aq_hw, u32 dma_sys_lbk);
 
 /* set rx traffic class mode */
-void rpb_rpf_rx_traf_class_mode_set(struct aq_hw_s *aq_hw,
-                                   u32 rx_traf_class_mode);
+void hw_atl_rpb_rpf_rx_traf_class_mode_set(struct aq_hw_s *aq_hw,
+                                          u32 rx_traf_class_mode);
 
 /* set rx buffer enable */
-void rpb_rx_buff_en_set(struct aq_hw_s *aq_hw, u32 rx_buff_en);
+void hw_atl_rpb_rx_buff_en_set(struct aq_hw_s *aq_hw, u32 rx_buff_en);
 
 /* set rx buffer high threshold (per tc) */
-void rpb_rx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw,
-                                        u32 rx_buff_hi_threshold_per_tc,
-                                        u32 buffer);
+void hw_atl_rpb_rx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw,
+                                               u32 rx_buff_hi_threshold_per_tc,
+                                               u32 buffer);
 
 /* set rx buffer low threshold (per tc) */
-void rpb_rx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw,
-                                        u32 rx_buff_lo_threshold_per_tc,
+void hw_atl_rpb_rx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw,
+                                               u32 rx_buff_lo_threshold_per_tc,
                                         u32 buffer);
 
 /* set rx flow control mode */
-void rpb_rx_flow_ctl_mode_set(struct aq_hw_s *aq_hw, u32 rx_flow_ctl_mode);
+void hw_atl_rpb_rx_flow_ctl_mode_set(struct aq_hw_s *aq_hw, u32 rx_flow_ctl_mode);
 
 /* set rx packet buffer size (per tc) */
-void rpb_rx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
-                                    u32 rx_pkt_buff_size_per_tc,
-                                    u32 buffer);
+void hw_atl_rpb_rx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
+                                           u32 rx_pkt_buff_size_per_tc,
+                                           u32 buffer);
 
 /* set rx xoff enable (per tc) */
-void rpb_rx_xoff_en_per_tc_set(struct aq_hw_s *aq_hw, u32 rx_xoff_en_per_tc,
-                              u32 buffer);
+void hw_atl_rpb_rx_xoff_en_per_tc_set(struct aq_hw_s *aq_hw, u32 rx_xoff_en_per_tc,
+                                     u32 buffer);
 
 /* rpf */
 
 /* set l2 broadcast count threshold */
-void rpfl2broadcast_count_threshold_set(struct aq_hw_s *aq_hw,
-                                       u32 l2broadcast_count_threshold);
+void hw_atl_rpfl2broadcast_count_threshold_set(struct aq_hw_s *aq_hw,
+                                              u32 l2broadcast_count_threshold);
 
 /* set l2 broadcast enable */
-void rpfl2broadcast_en_set(struct aq_hw_s *aq_hw, u32 l2broadcast_en);
+void hw_atl_rpfl2broadcast_en_set(struct aq_hw_s *aq_hw, u32 l2broadcast_en);
 
 /* set l2 broadcast filter action */
-void rpfl2broadcast_flr_act_set(struct aq_hw_s *aq_hw,
-                               u32 l2broadcast_flr_act);
+void hw_atl_rpfl2broadcast_flr_act_set(struct aq_hw_s *aq_hw,
+                                      u32 l2broadcast_flr_act);
 
 /* set l2 multicast filter enable */
-void rpfl2multicast_flr_en_set(struct aq_hw_s *aq_hw, u32 l2multicast_flr_en,
-                              u32 filter);
+void hw_atl_rpfl2multicast_flr_en_set(struct aq_hw_s *aq_hw,
+                                     u32 l2multicast_flr_en,
+                                     u32 filter);
 
 /* set l2 promiscuous mode enable */
-void rpfl2promiscuous_mode_en_set(struct aq_hw_s *aq_hw,
-                                 u32 l2promiscuous_mode_en);
+void hw_atl_rpfl2promiscuous_mode_en_set(struct aq_hw_s *aq_hw,
+                                        u32 l2promiscuous_mode_en);
 
 /* set l2 unicast filter action */
-void rpfl2unicast_flr_act_set(struct aq_hw_s *aq_hw, u32 l2unicast_flr_act,
-                             u32 filter);
+void hw_atl_rpfl2unicast_flr_act_set(struct aq_hw_s *aq_hw,
+                                    u32 l2unicast_flr_act,
+                                    u32 filter);
 
 /* set l2 unicast filter enable */
-void rpfl2_uc_flr_en_set(struct aq_hw_s *aq_hw, u32 l2unicast_flr_en,
-                        u32 filter);
+void hw_atl_rpfl2_uc_flr_en_set(struct aq_hw_s *aq_hw, u32 l2unicast_flr_en,
+                               u32 filter);
 
 /* set l2 unicast destination address lsw */
-void rpfl2unicast_dest_addresslsw_set(struct aq_hw_s *aq_hw,
-                                     u32 l2unicast_dest_addresslsw,
+void hw_atl_rpfl2unicast_dest_addresslsw_set(struct aq_hw_s *aq_hw,
+                                            u32 l2unicast_dest_addresslsw,
                                      u32 filter);
 
 /* set l2 unicast destination address msw */
-void rpfl2unicast_dest_addressmsw_set(struct aq_hw_s *aq_hw,
-                                     u32 l2unicast_dest_addressmsw,
+void hw_atl_rpfl2unicast_dest_addressmsw_set(struct aq_hw_s *aq_hw,
+                                            u32 l2unicast_dest_addressmsw,
                                      u32 filter);
 
 /* Set L2 Accept all Multicast packets */
-void rpfl2_accept_all_mc_packets_set(struct aq_hw_s *aq_hw,
-                                    u32 l2_accept_all_mc_packets);
+void hw_atl_rpfl2_accept_all_mc_packets_set(struct aq_hw_s *aq_hw,
+                                           u32 l2_accept_all_mc_packets);
 
 /* set user-priority tc mapping */
-void rpf_rpb_user_priority_tc_map_set(struct aq_hw_s *aq_hw,
-                                     u32 user_priority_tc_map, u32 tc);
+void hw_atl_rpf_rpb_user_priority_tc_map_set(struct aq_hw_s *aq_hw,
+                                            u32 user_priority_tc_map, u32 tc);
 
 /* set rss key address */
-void rpf_rss_key_addr_set(struct aq_hw_s *aq_hw, u32 rss_key_addr);
+void hw_atl_rpf_rss_key_addr_set(struct aq_hw_s *aq_hw, u32 rss_key_addr);
 
 /* set rss key write data */
-void rpf_rss_key_wr_data_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_data);
+void hw_atl_rpf_rss_key_wr_data_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_data);
 
 /* get rss key write enable */
-u32 rpf_rss_key_wr_en_get(struct aq_hw_s *aq_hw);
+u32 hw_atl_rpf_rss_key_wr_en_get(struct aq_hw_s *aq_hw);
 
 /* set rss key write enable */
-void rpf_rss_key_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_en);
+void hw_atl_rpf_rss_key_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_en);
 
 /* set rss redirection table address */
-void rpf_rss_redir_tbl_addr_set(struct aq_hw_s *aq_hw,
-                               u32 rss_redir_tbl_addr);
+void hw_atl_rpf_rss_redir_tbl_addr_set(struct aq_hw_s *aq_hw,
+                                      u32 rss_redir_tbl_addr);
 
 /* set rss redirection table write data */
-void rpf_rss_redir_tbl_wr_data_set(struct aq_hw_s *aq_hw,
-                                  u32 rss_redir_tbl_wr_data);
+void hw_atl_rpf_rss_redir_tbl_wr_data_set(struct aq_hw_s *aq_hw,
+                                         u32 rss_redir_tbl_wr_data);
 
 /* get rss redirection write enable */
-u32 rpf_rss_redir_wr_en_get(struct aq_hw_s *aq_hw);
+u32 hw_atl_rpf_rss_redir_wr_en_get(struct aq_hw_s *aq_hw);
 
 /* set rss redirection write enable */
-void rpf_rss_redir_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_redir_wr_en);
+void hw_atl_rpf_rss_redir_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_redir_wr_en);
 
 /* set tpo to rpf system loopback */
-void rpf_tpo_to_rpf_sys_lbk_set(struct aq_hw_s *aq_hw,
-                               u32 tpo_to_rpf_sys_lbk);
+void hw_atl_rpf_tpo_to_rpf_sys_lbk_set(struct aq_hw_s *aq_hw,
+                                      u32 tpo_to_rpf_sys_lbk);
 
 /* set vlan inner ethertype */
-void rpf_vlan_inner_etht_set(struct aq_hw_s *aq_hw, u32 vlan_inner_etht);
+void hw_atl_rpf_vlan_inner_etht_set(struct aq_hw_s *aq_hw, u32 vlan_inner_etht);
 
 /* set vlan outer ethertype */
-void rpf_vlan_outer_etht_set(struct aq_hw_s *aq_hw, u32 vlan_outer_etht);
+void hw_atl_rpf_vlan_outer_etht_set(struct aq_hw_s *aq_hw, u32 vlan_outer_etht);
 
 /* set vlan promiscuous mode enable */
-void rpf_vlan_prom_mode_en_set(struct aq_hw_s *aq_hw, u32 vlan_prom_mode_en);
+void hw_atl_rpf_vlan_prom_mode_en_set(struct aq_hw_s *aq_hw,
+                                     u32 vlan_prom_mode_en);
 
 /* Set VLAN untagged action */
-void rpf_vlan_untagged_act_set(struct aq_hw_s *aq_hw, u32 vlan_untagged_act);
+void hw_atl_rpf_vlan_untagged_act_set(struct aq_hw_s *aq_hw,
+                                     u32 vlan_untagged_act);
 
 /* Set VLAN accept untagged packets */
-void rpf_vlan_accept_untagged_packets_set(struct aq_hw_s *aq_hw,
-                                         u32 vlan_accept_untagged_packets);
+void hw_atl_rpf_vlan_accept_untagged_packets_set(struct aq_hw_s *aq_hw,
+                                                u32 vlan_acc_untagged_packets);
 
 /* Set VLAN filter enable */
-void rpf_vlan_flr_en_set(struct aq_hw_s *aq_hw, u32 vlan_flr_en, u32 filter);
+void hw_atl_rpf_vlan_flr_en_set(struct aq_hw_s *aq_hw, u32 vlan_flr_en,
+                               u32 filter);
 
 /* Set VLAN Filter Action */
-void rpf_vlan_flr_act_set(struct aq_hw_s *aq_hw, u32 vlan_filter_act,
-                         u32 filter);
+void hw_atl_rpf_vlan_flr_act_set(struct aq_hw_s *aq_hw, u32 vlan_filter_act,
+                                u32 filter);
 
 /* Set VLAN ID Filter */
-void rpf_vlan_id_flr_set(struct aq_hw_s *aq_hw, u32 vlan_id_flr, u32 filter);
+void hw_atl_rpf_vlan_id_flr_set(struct aq_hw_s *aq_hw, u32 vlan_id_flr,
+                               u32 filter);
 
 /* set ethertype filter enable */
-void rpf_etht_flr_en_set(struct aq_hw_s *aq_hw, u32 etht_flr_en, u32 filter);
+void hw_atl_rpf_etht_flr_en_set(struct aq_hw_s *aq_hw, u32 etht_flr_en,
+                               u32 filter);
 
 /* set  ethertype user-priority enable */
-void rpf_etht_user_priority_en_set(struct aq_hw_s *aq_hw,
-                                  u32 etht_user_priority_en, u32 filter);
+void hw_atl_rpf_etht_user_priority_en_set(struct aq_hw_s *aq_hw,
+                                         u32 etht_user_priority_en,
+                                         u32 filter);
 
 /* set  ethertype rx queue enable */
-void rpf_etht_rx_queue_en_set(struct aq_hw_s *aq_hw, u32 etht_rx_queue_en,
-                             u32 filter);
+void hw_atl_rpf_etht_rx_queue_en_set(struct aq_hw_s *aq_hw,
+                                    u32 etht_rx_queue_en,
+                                    u32 filter);
 
 /* set ethertype rx queue */
-void rpf_etht_rx_queue_set(struct aq_hw_s *aq_hw, u32 etht_rx_queue,
-                          u32 filter);
+void hw_atl_rpf_etht_rx_queue_set(struct aq_hw_s *aq_hw, u32 etht_rx_queue,
+                                 u32 filter);
 
 /* set ethertype user-priority */
-void rpf_etht_user_priority_set(struct aq_hw_s *aq_hw, u32 etht_user_priority,
-                               u32 filter);
+void hw_atl_rpf_etht_user_priority_set(struct aq_hw_s *aq_hw,
+                                      u32 etht_user_priority,
+                                      u32 filter);
 
 /* set ethertype management queue */
-void rpf_etht_mgt_queue_set(struct aq_hw_s *aq_hw, u32 etht_mgt_queue,
-                           u32 filter);
+void hw_atl_rpf_etht_mgt_queue_set(struct aq_hw_s *aq_hw, u32 etht_mgt_queue,
+                                  u32 filter);
 
 /* set ethertype filter action */
-void rpf_etht_flr_act_set(struct aq_hw_s *aq_hw, u32 etht_flr_act,
-                         u32 filter);
+void hw_atl_rpf_etht_flr_act_set(struct aq_hw_s *aq_hw, u32 etht_flr_act,
+                                u32 filter);
 
 /* set ethertype filter */
-void rpf_etht_flr_set(struct aq_hw_s *aq_hw, u32 etht_flr, u32 filter);
+void hw_atl_rpf_etht_flr_set(struct aq_hw_s *aq_hw, u32 etht_flr, u32 filter);
 
 /* rpo */
 
 /* set ipv4 header checksum offload enable */
-void rpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw,
-                                      u32 ipv4header_crc_offload_en);
+void hw_atl_rpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw,
+                                             u32 ipv4header_crc_offload_en);
 
 /* set rx descriptor vlan stripping */
-void rpo_rx_desc_vlan_stripping_set(struct aq_hw_s *aq_hw,
-                                   u32 rx_desc_vlan_stripping,
-                                   u32 descriptor);
+void hw_atl_rpo_rx_desc_vlan_stripping_set(struct aq_hw_s *aq_hw,
+                                          u32 rx_desc_vlan_stripping,
+                                          u32 descriptor);
 
 /* set tcp/udp checksum offload enable */
-void rpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw,
-                                   u32 tcp_udp_crc_offload_en);
+void hw_atl_rpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw,
+                                          u32 tcp_udp_crc_offload_en);
 
 /* Set LRO Patch Optimization Enable. */
-void rpo_lro_patch_optimization_en_set(struct aq_hw_s *aq_hw,
-                                      u32 lro_patch_optimization_en);
+void hw_atl_rpo_lro_patch_optimization_en_set(struct aq_hw_s *aq_hw,
+                                             u32 lro_patch_optimization_en);
 
 /* Set Large Receive Offload Enable */
-void rpo_lro_en_set(struct aq_hw_s *aq_hw, u32 lro_en);
+void hw_atl_rpo_lro_en_set(struct aq_hw_s *aq_hw, u32 lro_en);
 
 /* Set LRO Q Sessions Limit */
-void rpo_lro_qsessions_lim_set(struct aq_hw_s *aq_hw, u32 lro_qsessions_lim);
+void hw_atl_rpo_lro_qsessions_lim_set(struct aq_hw_s *aq_hw,
+                                     u32 lro_qsessions_lim);
 
 /* Set LRO Total Descriptor Limit */
-void rpo_lro_total_desc_lim_set(struct aq_hw_s *aq_hw, u32 lro_total_desc_lim);
+void hw_atl_rpo_lro_total_desc_lim_set(struct aq_hw_s *aq_hw,
+                                      u32 lro_total_desc_lim);
 
 /* Set LRO Min Payload of First Packet */
-void rpo_lro_min_pay_of_first_pkt_set(struct aq_hw_s *aq_hw,
-                                     u32 lro_min_pld_of_first_pkt);
+void hw_atl_rpo_lro_min_pay_of_first_pkt_set(struct aq_hw_s *aq_hw,
+                                            u32 lro_min_pld_of_first_pkt);
 
 /* Set LRO Packet Limit */
-void rpo_lro_pkt_lim_set(struct aq_hw_s *aq_hw, u32 lro_packet_lim);
+void hw_atl_rpo_lro_pkt_lim_set(struct aq_hw_s *aq_hw, u32 lro_packet_lim);
 
 /* Set LRO Max Number of Descriptors */
-void rpo_lro_max_num_of_descriptors_set(struct aq_hw_s *aq_hw,
-                                       u32 lro_max_desc_num, u32 lro);
+void hw_atl_rpo_lro_max_num_of_descriptors_set(struct aq_hw_s *aq_hw,
+                                              u32 lro_max_desc_num, u32 lro);
 
 /* Set LRO Time Base Divider */
-void rpo_lro_time_base_divider_set(struct aq_hw_s *aq_hw,
-                                  u32 lro_time_base_divider);
+void hw_atl_rpo_lro_time_base_divider_set(struct aq_hw_s *aq_hw,
+                                         u32 lro_time_base_divider);
 
 /*Set LRO Inactive Interval */
-void rpo_lro_inactive_interval_set(struct aq_hw_s *aq_hw,
-                                  u32 lro_inactive_interval);
+void hw_atl_rpo_lro_inactive_interval_set(struct aq_hw_s *aq_hw,
+                                         u32 lro_inactive_interval);
 
 /*Set LRO Max Coalescing Interval */
-void rpo_lro_max_coalescing_interval_set(struct aq_hw_s *aq_hw,
-                                        u32 lro_max_coalescing_interval);
+void hw_atl_rpo_lro_max_coalescing_interval_set(struct aq_hw_s *aq_hw,
+                                               u32 lro_max_coal_interval);
 
 /* rx */
 
 /* set rx register reset disable */
-void rx_rx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 rx_reg_res_dis);
+void hw_atl_rx_rx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 rx_reg_res_dis);
 
 /* tdm */
 
 /* set cpu id */
-void tdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca);
+void hw_atl_tdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca);
 
 /* set large send offload enable */
-void tdm_large_send_offload_en_set(struct aq_hw_s *aq_hw,
-                                  u32 large_send_offload_en);
+void hw_atl_tdm_large_send_offload_en_set(struct aq_hw_s *aq_hw,
+                                         u32 large_send_offload_en);
 
 /* set tx descriptor enable */
-void tdm_tx_desc_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_en, u32 descriptor);
+void hw_atl_tdm_tx_desc_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_en,
+                              u32 descriptor);
 
 /* set tx dca enable */
-void tdm_tx_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_dca_en);
+void hw_atl_tdm_tx_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_dca_en);
 
 /* set tx dca mode */
-void tdm_tx_dca_mode_set(struct aq_hw_s *aq_hw, u32 tx_dca_mode);
+void hw_atl_tdm_tx_dca_mode_set(struct aq_hw_s *aq_hw, u32 tx_dca_mode);
 
 /* set tx descriptor dca enable */
-void tdm_tx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_dca_en, u32 dca);
+void hw_atl_tdm_tx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_dca_en,
+                                  u32 dca);
 
 /* get tx descriptor head pointer */
-u32 tdm_tx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor);
+u32 hw_atl_tdm_tx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor);
 
 /* set tx descriptor length */
-void tdm_tx_desc_len_set(struct aq_hw_s *aq_hw, u32 tx_desc_len,
-                        u32 descriptor);
+void hw_atl_tdm_tx_desc_len_set(struct aq_hw_s *aq_hw, u32 tx_desc_len,
+                               u32 descriptor);
 
 /* set tx descriptor write-back interrupt enable */
-void tdm_tx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw,
-                                 u32 tx_desc_wr_wb_irq_en);
+void hw_atl_tdm_tx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw,
+                                        u32 tx_desc_wr_wb_irq_en);
 
 /* set tx descriptor write-back threshold */
-void tdm_tx_desc_wr_wb_threshold_set(struct aq_hw_s *aq_hw,
-                                    u32 tx_desc_wr_wb_threshold,
+void hw_atl_tdm_tx_desc_wr_wb_threshold_set(struct aq_hw_s *aq_hw,
+                                           u32 tx_desc_wr_wb_threshold,
                                     u32 descriptor);
 
 /* Set TDM Interrupt Moderation Enable */
-void tdm_tdm_intr_moder_en_set(struct aq_hw_s *aq_hw,
-                              u32 tdm_irq_moderation_en);
+void hw_atl_tdm_tdm_intr_moder_en_set(struct aq_hw_s *aq_hw,
+                                     u32 tdm_irq_moderation_en);
 /* thm */
 
 /* set lso tcp flag of first packet */
-void thm_lso_tcp_flag_of_first_pkt_set(struct aq_hw_s *aq_hw,
-                                      u32 lso_tcp_flag_of_first_pkt);
+void hw_atl_thm_lso_tcp_flag_of_first_pkt_set(struct aq_hw_s *aq_hw,
+                                             u32 lso_tcp_flag_of_first_pkt);
 
 /* set lso tcp flag of last packet */
-void thm_lso_tcp_flag_of_last_pkt_set(struct aq_hw_s *aq_hw,
-                                     u32 lso_tcp_flag_of_last_pkt);
+void hw_atl_thm_lso_tcp_flag_of_last_pkt_set(struct aq_hw_s *aq_hw,
+                                            u32 lso_tcp_flag_of_last_pkt);
 
 /* set lso tcp flag of middle packet */
-void thm_lso_tcp_flag_of_middle_pkt_set(struct aq_hw_s *aq_hw,
-                                       u32 lso_tcp_flag_of_middle_pkt);
+void hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(struct aq_hw_s *aq_hw,
+                                              u32 lso_tcp_flag_of_middle_pkt);
 
 /* tpb */
 
 /* set tx buffer enable */
-void tpb_tx_buff_en_set(struct aq_hw_s *aq_hw, u32 tx_buff_en);
+void hw_atl_tpb_tx_buff_en_set(struct aq_hw_s *aq_hw, u32 tx_buff_en);
 
 /* set tx buffer high threshold (per tc) */
-void tpb_tx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw,
-                                        u32 tx_buff_hi_threshold_per_tc,
+void hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw,
+                                               u32 tx_buff_hi_threshold_per_tc,
                                         u32 buffer);
 
 /* set tx buffer low threshold (per tc) */
-void tpb_tx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw,
-                                        u32 tx_buff_lo_threshold_per_tc,
+void hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw,
+                                               u32 tx_buff_lo_threshold_per_tc,
                                         u32 buffer);
 
 /* set tx dma system loopback enable */
-void tpb_tx_dma_sys_lbk_en_set(struct aq_hw_s *aq_hw, u32 tx_dma_sys_lbk_en);
+void hw_atl_tpb_tx_dma_sys_lbk_en_set(struct aq_hw_s *aq_hw, u32 tx_dma_sys_lbk_en);
 
 /* set tx packet buffer size (per tc) */
-void tpb_tx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
-                                    u32 tx_pkt_buff_size_per_tc, u32 buffer);
+void hw_atl_tpb_tx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
+                                           u32 tx_pkt_buff_size_per_tc, u32 buffer);
 
 /* set tx path pad insert enable */
-void tpb_tx_path_scp_ins_en_set(struct aq_hw_s *aq_hw, u32 tx_path_scp_ins_en);
+void hw_atl_tpb_tx_path_scp_ins_en_set(struct aq_hw_s *aq_hw, u32 tx_path_scp_ins_en);
 
 /* tpo */
 
 /* set ipv4 header checksum offload enable */
-void tpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw,
-                                      u32 ipv4header_crc_offload_en);
+void hw_atl_tpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw,
+                                             u32 ipv4header_crc_offload_en);
 
 /* set tcp/udp checksum offload enable */
-void tpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw,
-                                   u32 tcp_udp_crc_offload_en);
+void hw_atl_tpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw,
+                                          u32 tcp_udp_crc_offload_en);
 
 /* set tx pkt system loopback enable */
-void tpo_tx_pkt_sys_lbk_en_set(struct aq_hw_s *aq_hw, u32 tx_pkt_sys_lbk_en);
+void hw_atl_tpo_tx_pkt_sys_lbk_en_set(struct aq_hw_s *aq_hw,
+                                     u32 tx_pkt_sys_lbk_en);
 
 /* tps */
 
 /* set tx packet scheduler data arbitration mode */
-void tps_tx_pkt_shed_data_arb_mode_set(struct aq_hw_s *aq_hw,
-                                      u32 tx_pkt_shed_data_arb_mode);
+void hw_atl_tps_tx_pkt_shed_data_arb_mode_set(struct aq_hw_s *aq_hw,
+                                             u32 tx_pkt_shed_data_arb_mode);
 
 /* set tx packet scheduler descriptor rate current time reset */
-void tps_tx_pkt_shed_desc_rate_curr_time_res_set(struct aq_hw_s *aq_hw,
-                                                u32 curr_time_res);
+void hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(struct aq_hw_s *aq_hw,
+                                                       u32 curr_time_res);
 
 /* set tx packet scheduler descriptor rate limit */
-void tps_tx_pkt_shed_desc_rate_lim_set(struct aq_hw_s *aq_hw,
-                                      u32 tx_pkt_shed_desc_rate_lim);
+void hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(struct aq_hw_s *aq_hw,
+                                             u32 tx_pkt_shed_desc_rate_lim);
 
 /* set tx packet scheduler descriptor tc arbitration mode */
-void tps_tx_pkt_shed_desc_tc_arb_mode_set(struct aq_hw_s *aq_hw,
-                                         u32 tx_pkt_shed_desc_tc_arb_mode);
+void hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(struct aq_hw_s *aq_hw,
+                                                u32 arb_mode);
 
 /* set tx packet scheduler descriptor tc max credit */
-void tps_tx_pkt_shed_desc_tc_max_credit_set(struct aq_hw_s *aq_hw,
-                                           u32 tx_pkt_shed_desc_tc_max_credit,
+void hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(struct aq_hw_s *aq_hw,
+                                                  u32 max_credit,
                                            u32 tc);
 
 /* set tx packet scheduler descriptor tc weight */
-void tps_tx_pkt_shed_desc_tc_weight_set(struct aq_hw_s *aq_hw,
-                                       u32 tx_pkt_shed_desc_tc_weight,
+void hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(struct aq_hw_s *aq_hw,
+                                              u32 tx_pkt_shed_desc_tc_weight,
                                        u32 tc);
 
 /* set tx packet scheduler descriptor vm arbitration mode */
-void tps_tx_pkt_shed_desc_vm_arb_mode_set(struct aq_hw_s *aq_hw,
-                                         u32 tx_pkt_shed_desc_vm_arb_mode);
+void hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(struct aq_hw_s *aq_hw,
+                                                u32 arb_mode);
 
 /* set tx packet scheduler tc data max credit */
-void tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw_s *aq_hw,
-                                           u32 tx_pkt_shed_tc_data_max_credit,
+void hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw_s *aq_hw,
+                                                  u32 max_credit,
                                            u32 tc);
 
 /* set tx packet scheduler tc data weight */
-void tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw_s *aq_hw,
-                                       u32 tx_pkt_shed_tc_data_weight,
+void hw_atl_tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw_s *aq_hw,
+                                              u32 tx_pkt_shed_tc_data_weight,
                                        u32 tc);
 
 /* tx */
 
 /* set tx register reset disable */
-void tx_tx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 tx_reg_res_dis);
+void hw_atl_tx_tx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 tx_reg_res_dis);
 
 /* msm */
 
 /* get register access status */
-u32 msm_reg_access_status_get(struct aq_hw_s *aq_hw);
+u32 hw_atl_msm_reg_access_status_get(struct aq_hw_s *aq_hw);
 
 /* set  register address for indirect address */
-void msm_reg_addr_for_indirect_addr_set(struct aq_hw_s *aq_hw,
-                                       u32 reg_addr_for_indirect_addr);
+void hw_atl_msm_reg_addr_for_indirect_addr_set(struct aq_hw_s *aq_hw,
+                                              u32 reg_addr_for_indirect_addr);
 
 /* set register read strobe */
-void msm_reg_rd_strobe_set(struct aq_hw_s *aq_hw, u32 reg_rd_strobe);
+void hw_atl_msm_reg_rd_strobe_set(struct aq_hw_s *aq_hw, u32 reg_rd_strobe);
 
 /* get  register read data */
-u32 msm_reg_rd_data_get(struct aq_hw_s *aq_hw);
+u32 hw_atl_msm_reg_rd_data_get(struct aq_hw_s *aq_hw);
 
 /* set  register write data */
-void msm_reg_wr_data_set(struct aq_hw_s *aq_hw, u32 reg_wr_data);
+void hw_atl_msm_reg_wr_data_set(struct aq_hw_s *aq_hw, u32 reg_wr_data);
 
 /* set register write strobe */
-void msm_reg_wr_strobe_set(struct aq_hw_s *aq_hw, u32 reg_wr_strobe);
+void hw_atl_msm_reg_wr_strobe_set(struct aq_hw_s *aq_hw, u32 reg_wr_strobe);
 
 /* pci */
 
 /* set pci register reset disable */
-void pci_pci_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 pci_reg_res_dis);
+void hw_atl_pci_pci_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 pci_reg_res_dis);
 
 #endif /* HW_ATL_LLH_H */
index 0abb7d788db22d53782c5d553d348c1ffc70f8d3..9c7e9161b4db9204900d1d9b3dd1de6e92e170f1 100644 (file)
@@ -35,15 +35,15 @@ static int hw_atl_utils_fw_downld_dwords(struct aq_hw_s *self, u32 a,
 {
        int err = 0;
 
-       AQ_HW_WAIT_FOR(reg_glb_cpu_sem_get(self,
-                                          HW_ATL_FW_SM_RAM) == 1U,
-                                          1U, 10000U);
+       AQ_HW_WAIT_FOR(hw_atl_reg_glb_cpu_sem_get(self,
+                                                 HW_ATL_FW_SM_RAM) == 1U,
+                                                 1U, 10000U);
 
        if (err < 0) {
                bool is_locked;
 
-               reg_glb_cpu_sem_set(self, 1U, HW_ATL_FW_SM_RAM);
-               is_locked = reg_glb_cpu_sem_get(self, HW_ATL_FW_SM_RAM);
+               hw_atl_reg_glb_cpu_sem_set(self, 1U, HW_ATL_FW_SM_RAM);
+               is_locked = hw_atl_reg_glb_cpu_sem_get(self, HW_ATL_FW_SM_RAM);
                if (!is_locked) {
                        err = -ETIME;
                        goto err_exit;
@@ -64,7 +64,7 @@ static int hw_atl_utils_fw_downld_dwords(struct aq_hw_s *self, u32 a,
                *(p++) = aq_hw_read_reg(self, 0x0000020CU);
        }
 
-       reg_glb_cpu_sem_set(self, 1U, HW_ATL_FW_SM_RAM);
+       hw_atl_reg_glb_cpu_sem_set(self, 1U, HW_ATL_FW_SM_RAM);
 
 err_exit:
        return err;
@@ -76,7 +76,7 @@ static int hw_atl_utils_fw_upload_dwords(struct aq_hw_s *self, u32 a, u32 *p,
        int err = 0;
        bool is_locked;
 
-       is_locked = reg_glb_cpu_sem_get(self, HW_ATL_FW_SM_RAM);
+       is_locked = hw_atl_reg_glb_cpu_sem_get(self, HW_ATL_FW_SM_RAM);
        if (!is_locked) {
                err = -ETIME;
                goto err_exit;
@@ -95,7 +95,7 @@ static int hw_atl_utils_fw_upload_dwords(struct aq_hw_s *self, u32 a, u32 *p,
                }
        }
 
-       reg_glb_cpu_sem_set(self, 1U, HW_ATL_FW_SM_RAM);
+       hw_atl_reg_glb_cpu_sem_set(self, 1U, HW_ATL_FW_SM_RAM);
 
 err_exit:
        return err;
@@ -131,7 +131,7 @@ static int hw_atl_utils_init_ucp(struct aq_hw_s *self,
                aq_hw_write_reg(self, HW_ATL_UCP_0X370_REG, ucp_0x370);
        }
 
-       reg_glb_cpu_scratch_scp_set(self, 0x00000000U, 25U);
+       hw_atl_reg_glb_cpu_scratch_scp_set(self, 0x00000000U, 25U);
 
        /* check 10 times by 1ms */
        AQ_HW_WAIT_FOR(0U != (self->mbox_addr =
@@ -280,7 +280,7 @@ void hw_atl_utils_mpi_read_stats(struct aq_hw_s *self,
                pmbox->stats.ubtc = pmbox->stats.uptc * mtu;
                pmbox->stats.dpc = atomic_read(&self->dpc);
        } else {
-               pmbox->stats.dpc = reg_rx_dma_stat_counter7get(self);
+               pmbox->stats.dpc = hw_atl_reg_rx_dma_stat_counter7get(self);
        }
 
 err_exit:;
@@ -461,7 +461,7 @@ unsigned int hw_atl_utils_mbps_2_speed_index(unsigned int mbps)
 void hw_atl_utils_hw_chip_features_init(struct aq_hw_s *self, u32 *p)
 {
        u32 chip_features = 0U;
-       u32 val = reg_glb_mif_id_get(self);
+       u32 val = hw_atl_reg_glb_mif_id_get(self);
        u32 mif_rev = val & 0xFFU;
 
        if ((3U & mif_rev) == 1U) {
@@ -523,10 +523,10 @@ int hw_atl_utils_update_stats(struct aq_hw_s *self)
                AQ_SDELTA(dpc);
        }
 #undef AQ_SDELTA
-       self->curr_stats.dma_pkt_rc = stats_rx_dma_good_pkt_counterlsw_get(self);
-       self->curr_stats.dma_pkt_tc = stats_tx_dma_good_pkt_counterlsw_get(self);
-       self->curr_stats.dma_oct_rc = stats_rx_dma_good_octet_counterlsw_get(self);
-       self->curr_stats.dma_oct_tc = stats_tx_dma_good_octet_counterlsw_get(self);
+       self->curr_stats.dma_pkt_rc = hw_atl_stats_rx_dma_good_pkt_counterlsw_get(self);
+       self->curr_stats.dma_pkt_tc = hw_atl_stats_tx_dma_good_pkt_counterlsw_get(self);
+       self->curr_stats.dma_oct_rc = hw_atl_stats_rx_dma_good_octet_counterlsw_get(self);
+       self->curr_stats.dma_oct_tc = hw_atl_stats_tx_dma_good_octet_counterlsw_get(self);
 
        memcpy(&self->last_stats, &mbox.stats, sizeof(mbox.stats));