net: dsa: microchip: lan9371/2: add 100BaseTX PHY support

On the LAN9371 and LAN9372, the 4th internal PHY is a 100BaseTX PHY
instead of a 100BaseT1 PHY. The 100BaseTX PHYs have a different base
register offset.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Acked-by: Arun Ramadoss <arun.ramadoss@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/dsa/microchip/ksz_common.h b/drivers/net/dsa/microchip/ksz_common.h
index ee7db46e469d59425d71c2bac9a977b75c293999..c4a4664c0385984c7e7082737659401b0ef9b252 100644 (file)
--- a/drivers/net/dsa/microchip/ksz_common.h
+++ b/drivers/net/dsa/microchip/ksz_common.h
@@ -22,6 +22,7 @@
 /* all KSZ switches count ports from 1 */
 #define KSZ_PORT_1 0
 #define KSZ_PORT_2 1
+#define KSZ_PORT_4 3
 
 struct ksz_device;
 struct ksz_port;

diff --git a/drivers/net/dsa/microchip/lan937x_main.c b/drivers/net/dsa/microchip/lan937x_main.c
index b479a628b1ae5610990b2bc56f06656ee2ee798c..eaa862eb6b265c9c2537cd95881e89fed6d3279c 100644 (file)
--- a/drivers/net/dsa/microchip/lan937x_main.c
+++ b/drivers/net/dsa/microchip/lan937x_main.c
@@ -55,6 +55,10 @@ static int lan937x_vphy_ind_addr_wr(struct ksz_device *dev, int addr, int reg)
        u16 addr_base = REG_PORT_T1_PHY_CTRL_BASE;
        u16 temp;
 
+       if ((dev->info->chip_id == LAN9371_CHIP_ID ||
+            dev->info->chip_id == LAN9372_CHIP_ID) && addr == KSZ_PORT_4)
+               addr_base = REG_PORT_TX_PHY_CTRL_BASE;
+
        /* get register address based on the logical port */
        temp = PORT_CTRL_ADDR(addr, (addr_base + (reg << 2)));
 

diff --git a/drivers/net/dsa/microchip/lan937x_reg.h b/drivers/net/dsa/microchip/lan937x_reg.h
index 45b606b6429f65c5ad110e139e77fe38b2aacb98..7ecada9240233315d531e8b9711598707382a1aa 100644 (file)
--- a/drivers/net/dsa/microchip/lan937x_reg.h
+++ b/drivers/net/dsa/microchip/lan937x_reg.h
@@ -147,6 +147,7 @@
 
 /* 1 - Phy */
 #define REG_PORT_T1_PHY_CTRL_BASE      0x0100
+#define REG_PORT_TX_PHY_CTRL_BASE      0x0280
 
 /* 3 - xMII */
 #define PORT_SGMII_SEL                 BIT(7)