net/mlx5: Expose shared buffer registers bits and structs

Add the shared receive buffer management and configuration registers:
1. SBPR - Shared Buffer Pools Register
2. SBCM - Shared Buffer Class Management Register

Signed-off-by: Maher Sanalla <msanalla@nvidia.com>
Reviewed-by: Moshe Shemesh <moshe@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>

diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h
index d476255c9a3f0d9ea7f0dcd3c8231fbcd9e30d3e..0c4f6acf59ca8d5bdc18863fce0db7c7c009401d 100644 (file)
--- a/include/linux/mlx5/driver.h
+++ b/include/linux/mlx5/driver.h
@@ -100,6 +100,8 @@ enum {
 };
 
 enum {
+       MLX5_REG_SBPR            = 0xb001,
+       MLX5_REG_SBCM            = 0xb002,
        MLX5_REG_QPTS            = 0x4002,
        MLX5_REG_QETCR           = 0x4005,
        MLX5_REG_QTCT            = 0x400a,

diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index a9ee7bc59c90199126d15ed61dbc20248846c0c0..a84bdeeed2c674ae38675c7d0ae659e2196b137b 100644 (file)
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -11000,6 +11000,67 @@ struct mlx5_ifc_pbmc_reg_bits {
        u8         reserved_at_2e0[0x80];
 };
 
+struct mlx5_ifc_sbpr_reg_bits {
+       u8         desc[0x1];
+       u8         snap[0x1];
+       u8         reserved_at_2[0x4];
+       u8         dir[0x2];
+       u8         reserved_at_8[0x14];
+       u8         pool[0x4];
+
+       u8         infi_size[0x1];
+       u8         reserved_at_21[0x7];
+       u8         size[0x18];
+
+       u8         reserved_at_40[0x1c];
+       u8         mode[0x4];
+
+       u8         reserved_at_60[0x8];
+       u8         buff_occupancy[0x18];
+
+       u8         clr[0x1];
+       u8         reserved_at_81[0x7];
+       u8         max_buff_occupancy[0x18];
+
+       u8         reserved_at_a0[0x8];
+       u8         ext_buff_occupancy[0x18];
+};
+
+struct mlx5_ifc_sbcm_reg_bits {
+       u8         desc[0x1];
+       u8         snap[0x1];
+       u8         reserved_at_2[0x6];
+       u8         local_port[0x8];
+       u8         pnat[0x2];
+       u8         pg_buff[0x6];
+       u8         reserved_at_18[0x6];
+       u8         dir[0x2];
+
+       u8         reserved_at_20[0x1f];
+       u8         exc[0x1];
+
+       u8         reserved_at_40[0x40];
+
+       u8         reserved_at_80[0x8];
+       u8         buff_occupancy[0x18];
+
+       u8         clr[0x1];
+       u8         reserved_at_a1[0x7];
+       u8         max_buff_occupancy[0x18];
+
+       u8         reserved_at_c0[0x8];
+       u8         min_buff[0x18];
+
+       u8         infi_max[0x1];
+       u8         reserved_at_e1[0x7];
+       u8         max_buff[0x18];
+
+       u8         reserved_at_100[0x20];
+
+       u8         reserved_at_120[0x1c];
+       u8         pool[0x4];
+};
+
 struct mlx5_ifc_qtct_reg_bits {
        u8         reserved_at_0[0x8];
        u8         port_number[0x8];