perf: arm_cspmu: Split 64-bit write to 32-bit writes

Split the 64-bit register accesses if 64-bit access is not supported
by the PMU.

Signed-off-by: Ilkka Koskinen <ilkka@os.amperecomputing.com>
Reviewed-by: Besar Wicaksono <bwicaksono@nvidia.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20230913233941.9814-2-ilkka@os.amperecomputing.com
Signed-off-by: Will Deacon <will@kernel.org>

diff --git a/drivers/perf/arm_cspmu/arm_cspmu.c b/drivers/perf/arm_cspmu/arm_cspmu.c
index c59f1e5a35a335d5a4914c875cbed58380dd882f..5f4f04135a22d95046adef60cbc7467fc7a9812c 100644 (file)
--- a/drivers/perf/arm_cspmu/arm_cspmu.c
+++ b/drivers/perf/arm_cspmu/arm_cspmu.c
@@ -719,7 +719,10 @@ static void arm_cspmu_write_counter(struct perf_event *event, u64 val)
        if (use_64b_counter_reg(cspmu)) {
                offset = counter_offset(sizeof(u64), event->hw.idx);
 
-               writeq(val, cspmu->base1 + offset);
+               if (cspmu->has_atomic_dword)
+                       writeq(val, cspmu->base1 + offset);
+               else
+                       lo_hi_writeq(val, cspmu->base1 + offset);
        } else {
                offset = counter_offset(sizeof(u32), event->hw.idx);