drm/i915/pxp/mtl: Update pxp-firmware response timeout

Update the max GSC-fw response time to match updated internal
fw specs. Because this response time is an SLA on the firmware,
not inclusive of i915->GuC->HW handoff latency, when submitting
requests to the GSC fw via intel_gsc_uc_heci_cmd_submit helpers,
start the count after the request hits the GSC command streamer.
Also, move GSC_REPLY_LATENCY_MS definition from pxp header to
intel_gsc_uc_heci_cmd_submit.h since its for any GSC HECI packet.

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
Reviewed-by: Vivaik Balasubrawmanian <vivaik.balasubrawmanian@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230917211933.1407559-2-alan.previn.teres.alexis@intel.com

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c
index 89ed5ee9cdedca4187e318bd937992e26201275c..2fde5c360cffde7c2d008f0038193015d9f2456c 100644 (file)
--- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c
@@ -81,8 +81,17 @@ out_rq:
 
        i915_request_add(rq);
 
-       if (!err && i915_request_wait(rq, 0, msecs_to_jiffies(500)) < 0)
-               err = -ETIME;
+       if (!err) {
+               /*
+                * Start timeout for i915_request_wait only after considering one possible
+                * pending GSC-HECI submission cycle on the other (non-privileged) path.
+                */
+               if (wait_for(i915_request_started(rq), GSC_HECI_REPLY_LATENCY_MS))
+                       drm_dbg(&gsc_uc_to_gt(gsc)->i915->drm,
+                               "Delay in gsc-heci-priv submission to gsccs-hw");
+               if (i915_request_wait(rq, 0, msecs_to_jiffies(GSC_HECI_REPLY_LATENCY_MS)) < 0)
+                       err = -ETIME;
+       }
 
        i915_request_put(rq);
 
@@ -186,6 +195,13 @@ out_rq:
        i915_request_add(rq);
 
        if (!err) {
+               /*
+                * Start timeout for i915_request_wait only after considering one possible
+                * pending GSC-HECI submission cycle on the other (privileged) path.
+                */
+               if (wait_for(i915_request_started(rq), GSC_HECI_REPLY_LATENCY_MS))
+                       drm_dbg(&gsc_uc_to_gt(gsc)->i915->drm,
+                               "Delay in gsc-heci-non-priv submission to gsccs-hw");
                if (i915_request_wait(rq, I915_WAIT_INTERRUPTIBLE,
                                      msecs_to_jiffies(timeout_ms)) < 0)
                        err = -ETIME;

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h
index 09d3fbdad05a537e99410378e03052827d11c3cc..c4308291c003ff56e6217071382a82b50b5c4674 100644 (file)
--- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h
@@ -12,6 +12,12 @@ struct i915_vma;
 struct intel_context;
 struct intel_gsc_uc;
 
+#define GSC_HECI_REPLY_LATENCY_MS 500
+/*
+ * Max FW response time is 500ms, but this should be counted from the time the
+ * command has hit the GSC-CS hardware, not the preceding handoff to GuC CTB.
+ */
+
 struct intel_gsc_mtl_header {
        u32 validity_marker;
 #define GSC_HECI_VALIDITY_MARKER 0xA578875A

diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c b/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c
index 2a600184a0771030600e34cc90a85c553adfae8f..9b2cc0db2f5550eb1880ed3bee65cfefbcd30372 100644 (file)
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c
@@ -111,7 +111,7 @@ gsccs_send_message(struct intel_pxp *pxp,
 
        ret = intel_gsc_uc_heci_cmd_submit_nonpriv(&gt->uc.gsc,
                                                   exec_res->ce, &pkt, exec_res->bb_vaddr,
-                                                  GSC_REPLY_LATENCY_MS);
+                                                  GSC_HECI_REPLY_LATENCY_MS);
        if (ret) {
                drm_err(&i915->drm, "failed to send gsc PXP msg (%d)\n", ret);
                goto unlock;

diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h b/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h
index 298ad38e6c7df634886a002e9046bae145fb7f08..9aae779c4da31885f137008f818e4926fa874348 100644 (file)
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h
@@ -8,16 +8,14 @@
 
 #include <linux/types.h>
 
+#include "gt/uc/intel_gsc_uc_heci_cmd_submit.h"
+
 struct intel_pxp;
 
-#define GSC_REPLY_LATENCY_MS 210
-/*
- * Max FW response time is 200ms, to which we add 10ms to account for overhead
- * such as request preparation, GuC submission to hw and pipeline completion times.
- */
 #define GSC_PENDING_RETRY_MAXCOUNT 40
 #define GSC_PENDING_RETRY_PAUSE_MS 50
-#define GSCFW_MAX_ROUND_TRIP_LATENCY_MS (GSC_PENDING_RETRY_MAXCOUNT * GSC_PENDING_RETRY_PAUSE_MS)
+#define GSCFW_MAX_ROUND_TRIP_LATENCY_MS (GSC_HECI_REPLY_LATENCY_MS + \
+                                        (GSC_PENDING_RETRY_MAXCOUNT * GSC_PENDING_RETRY_PAUSE_MS))
 
 #ifdef CONFIG_DRM_I915_PXP
 void intel_pxp_gsccs_fini(struct intel_pxp *pxp);