crypto: qce - support zero length test vectors

crypto test module passes zero length vectors as test input to sha-1 and
sha-256. To provide correct output for these vectors, hash zero support
has been added as in other crypto drivers.

Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 802b9ada4e9e9982a2f7f1266855a10189603a73..7bc58bf9970359dc43071d15cdde9e2ee127f024 100644 (file)
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -624,6 +624,8 @@ config CRYPTO_DEV_QCE_SKCIPHER
 config CRYPTO_DEV_QCE_SHA
        bool
        depends on CRYPTO_DEV_QCE
+       select CRYPTO_SHA1
+       select CRYPTO_SHA256
 
 choice
        prompt "Algorithms enabled for QCE acceleration"

diff --git a/drivers/crypto/qce/common.h b/drivers/crypto/qce/common.h
index 9f989cba0f1b56bd086dd79bde7c738b60e31ff8..85ba16418a049ec373058a2e25511c5764075f09 100644 (file)
--- a/drivers/crypto/qce/common.h
+++ b/drivers/crypto/qce/common.h
@@ -87,6 +87,8 @@ struct qce_alg_template {
                struct ahash_alg ahash;
        } alg;
        struct qce_device *qce;
+       const u8 *hash_zero;
+       const u32 digest_size;
 };
 
 void qce_cpu_to_be32p_array(__be32 *dst, const u8 *src, unsigned int len);

diff --git a/drivers/crypto/qce/sha.c b/drivers/crypto/qce/sha.c
index 1ab62e7d5f3cbc726001dbbdd8e98e789e4943b1..ed82520203f94fe6ff9cbafceee93795e2df1eb7 100644 (file)
--- a/drivers/crypto/qce/sha.c
+++ b/drivers/crypto/qce/sha.c
@@ -305,8 +305,12 @@ static int qce_ahash_final(struct ahash_request *req)
        struct qce_alg_template *tmpl = to_ahash_tmpl(req->base.tfm);
        struct qce_device *qce = tmpl->qce;
 
-       if (!rctx->buflen)
+       if (!rctx->buflen) {
+               if (tmpl->hash_zero)
+                       memcpy(req->result, tmpl->hash_zero,
+                                       tmpl->alg.ahash.halg.digestsize);
                return 0;
+       }
 
        rctx->last_blk = true;
 
@@ -338,6 +342,13 @@ static int qce_ahash_digest(struct ahash_request *req)
        rctx->first_blk = true;
        rctx->last_blk = true;
 
+       if (!rctx->nbytes_orig) {
+               if (tmpl->hash_zero)
+                       memcpy(req->result, tmpl->hash_zero,
+                                       tmpl->alg.ahash.halg.digestsize);
+               return 0;
+       }
+
        return qce->async_req_enqueue(tmpl->qce, &req->base);
 }
 
@@ -490,6 +501,11 @@ static int qce_ahash_register_one(const struct qce_ahash_def *def,
        alg->halg.digestsize = def->digestsize;
        alg->halg.statesize = def->statesize;
 
+       if (IS_SHA1(def->flags))
+               tmpl->hash_zero = sha1_zero_message_hash;
+       else if (IS_SHA256(def->flags))
+               tmpl->hash_zero = sha256_zero_message_hash;
+
        base = &alg->halg.base;
        base->cra_blocksize = def->blocksize;
        base->cra_priority = 300;