arm64: dts: qcom: sm8450: Supply clock from cpufreq node to CPUs

Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks
to the CPU cores. But this relationship is not represented in DTS so far.

So let's make cpufreq node as the clock provider and CPU nodes as the
consumers. The clock index for each CPU node is based on the frequency
domain index.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221117053145.10409-3-manivannan.sadhasivam@linaro.org

diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 09135edb2b9f812c9f668fd10671bb1b7c574bbf..b3f826e652bc083cc6ee380b5f87cc3bda02d15c 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -52,6 +52,7 @@
                        power-domain-names = "psci";
                        qcom,freq-domain = <&cpufreq_hw 0>;
                        #cooling-cells = <2>;
+                       clocks = <&cpufreq_hw 0>;
                        L2_0: l2-cache {
                              compatible = "cache";
                              next-level-cache = <&L3_0>;
@@ -71,6 +72,7 @@
                        power-domain-names = "psci";
                        qcom,freq-domain = <&cpufreq_hw 0>;
                        #cooling-cells = <2>;
+                       clocks = <&cpufreq_hw 0>;
                        L2_100: l2-cache {
                              compatible = "cache";
                              next-level-cache = <&L3_0>;
@@ -87,6 +89,7 @@
                        power-domain-names = "psci";
                        qcom,freq-domain = <&cpufreq_hw 0>;
                        #cooling-cells = <2>;
+                       clocks = <&cpufreq_hw 0>;
                        L2_200: l2-cache {
                              compatible = "cache";
                              next-level-cache = <&L3_0>;
@@ -103,6 +106,7 @@
                        power-domain-names = "psci";
                        qcom,freq-domain = <&cpufreq_hw 0>;
                        #cooling-cells = <2>;
+                       clocks = <&cpufreq_hw 0>;
                        L2_300: l2-cache {
                              compatible = "cache";
                              next-level-cache = <&L3_0>;
@@ -119,6 +123,7 @@
                        power-domain-names = "psci";
                        qcom,freq-domain = <&cpufreq_hw 1>;
                        #cooling-cells = <2>;
+                       clocks = <&cpufreq_hw 1>;
                        L2_400: l2-cache {
                              compatible = "cache";
                              next-level-cache = <&L3_0>;
@@ -135,6 +140,7 @@
                        power-domain-names = "psci";
                        qcom,freq-domain = <&cpufreq_hw 1>;
                        #cooling-cells = <2>;
+                       clocks = <&cpufreq_hw 1>;
                        L2_500: l2-cache {
                              compatible = "cache";
                              next-level-cache = <&L3_0>;
@@ -152,6 +158,7 @@
                        power-domain-names = "psci";
                        qcom,freq-domain = <&cpufreq_hw 1>;
                        #cooling-cells = <2>;
+                       clocks = <&cpufreq_hw 1>;
                        L2_600: l2-cache {
                              compatible = "cache";
                              next-level-cache = <&L3_0>;
@@ -168,6 +175,7 @@
                        power-domain-names = "psci";
                        qcom,freq-domain = <&cpufreq_hw 2>;
                        #cooling-cells = <2>;
+                       clocks = <&cpufreq_hw 2>;
                        L2_700: l2-cache {
                              compatible = "cache";
                              next-level-cache = <&L3_0>;
@@ -3259,6 +3267,7 @@
                                     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
                        #freq-domain-cells = <1>;
+                       #clock-cells = <1>;
                };
 
                gem_noc: interconnect@19100000 {