drm/bridge: nwl-dsi: Use vsync/hsync polarity from display mode

Using the correct bit helps. The documentation specifies bit 0 in both
registers to be controlling polarity of dpi_vsync_input and
dpi_hsync_input polarity. Bit 1 is reserved, and should therefore not be
set.

Tested with panel that requires active high vsync and hsync.

Signed-off-by: Esben Haabendal <esben@geanix.com>
Reviewed-by: Robert Foss <rfoss@kernel.org>
Signed-off-by: Robert Foss <rfoss@kernel.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20240814-nwl-dsi-sync-polarity-v1-1-ee198e369196@geanix.com

diff --git a/drivers/gpu/drm/bridge/nwl-dsi.c b/drivers/gpu/drm/bridge/nwl-dsi.c
index 8d54091ec66e4ef66d5d8a262f0c5aecd5676898..5f05647a3beabcfdee458de9135342069f8e18be 100644 (file)
--- a/drivers/gpu/drm/bridge/nwl-dsi.c
+++ b/drivers/gpu/drm/bridge/nwl-dsi.c
@@ -289,13 +289,13 @@ static int nwl_dsi_config_dpi(struct nwl_dsi *dsi)
 
        nwl_dsi_write(dsi, NWL_DSI_INTERFACE_COLOR_CODING, NWL_DSI_DPI_24_BIT);
        nwl_dsi_write(dsi, NWL_DSI_PIXEL_FORMAT, color_format);
-       /*
-        * Adjusting input polarity based on the video mode results in
-        * a black screen so always pick active low:
-        */
        nwl_dsi_write(dsi, NWL_DSI_VSYNC_POLARITY,
+                     dsi->mode.flags & DRM_MODE_FLAG_PVSYNC ?
+                     NWL_DSI_VSYNC_POLARITY_ACTIVE_HIGH :
                      NWL_DSI_VSYNC_POLARITY_ACTIVE_LOW);
        nwl_dsi_write(dsi, NWL_DSI_HSYNC_POLARITY,
+                     dsi->mode.flags & DRM_MODE_FLAG_PHSYNC ?
+                     NWL_DSI_HSYNC_POLARITY_ACTIVE_HIGH :
                      NWL_DSI_HSYNC_POLARITY_ACTIVE_LOW);
 
        burst_mode = (dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_BURST) &&

diff --git a/drivers/gpu/drm/bridge/nwl-dsi.h b/drivers/gpu/drm/bridge/nwl-dsi.h
index a247a8a11c7cbf5f8c76bb8e44b3a5a90c2d5da9..61e7d65cb1eb254ec6636f8e73a7c35d7a11a266 100644 (file)
--- a/drivers/gpu/drm/bridge/nwl-dsi.h
+++ b/drivers/gpu/drm/bridge/nwl-dsi.h
@@ -30,11 +30,11 @@
 #define NWL_DSI_PIXEL_FORMAT                   0x20c
 #define NWL_DSI_VSYNC_POLARITY                 0x210
 #define NWL_DSI_VSYNC_POLARITY_ACTIVE_LOW      0
-#define NWL_DSI_VSYNC_POLARITY_ACTIVE_HIGH     BIT(1)
+#define NWL_DSI_VSYNC_POLARITY_ACTIVE_HIGH     BIT(0)
 
 #define NWL_DSI_HSYNC_POLARITY                 0x214
 #define NWL_DSI_HSYNC_POLARITY_ACTIVE_LOW      0
-#define NWL_DSI_HSYNC_POLARITY_ACTIVE_HIGH     BIT(1)
+#define NWL_DSI_HSYNC_POLARITY_ACTIVE_HIGH     BIT(0)
 
 #define NWL_DSI_VIDEO_MODE                     0x218
 #define NWL_DSI_HFP                            0x21c