spi-nand/spi-mem DTR support

Merge series from Miquel Raynal <miquel.raynal@bootlin.com>:

Here is a (big) series supposed to bring DTR support in SPI-NAND.

diff --cc drivers/spi/spi-cadence-quadspi.c
Simple merge

diff --cc drivers/spi/spi-rockchip-sfc.c
index 59de351499a0813077cf5c7b7ddd1286e13d22b0,0cf0e1d3fbae3ada78843829a789c6c9931d54a0..f3fe10eddb6accef966a60a47e9fa64bc25bbc89
--- 1/drivers/spi/spi-rockchip-sfc.c
--- 2/drivers/spi/spi-rockchip-sfc.c
+++ b/drivers/spi/spi-rockchip-sfc.c
@@@ -526,22 -491,14 +526,22 @@@ static int rockchip_sfc_exec_mem_op(str
        struct rockchip_sfc *sfc = spi_controller_get_devdata(mem->spi->controller);
        u32 len = op->data.nbytes;
        int ret;
 +      u8 cs = spi_get_chipselect(mem->spi, 0);
  
 -      if (unlikely(op->max_freq != sfc->frequency)) {
 -              ret = clk_set_rate(sfc->clk, op->max_freq);
 +      ret = pm_runtime_get_sync(sfc->dev);
 +      if (ret < 0) {
 +              pm_runtime_put_noidle(sfc->dev);
 +              return ret;
 +      }
 +
-       if (unlikely(mem->spi->max_speed_hz != sfc->speed[cs]) &&
++      if (unlikely(op->max_freq != sfc->speed[cs]) &&
 +          !has_acpi_companion(sfc->dev)) {
-               ret = rockchip_sfc_clk_set_rate(sfc, mem->spi->max_speed_hz);
++              ret = rockchip_sfc_clk_set_rate(sfc, op->max_freq);
                if (ret)
 -                      return ret;
 -              sfc->frequency = op->max_freq;
 +                      goto out;
-               sfc->speed[cs] = mem->spi->max_speed_hz;
++              sfc->speed[cs] = op->max_freq;
                dev_dbg(sfc->dev, "set_freq=%dHz real_freq=%ldHz\n",
 -                      sfc->frequency, clk_get_rate(sfc->clk));
 +                      sfc->speed[cs], rockchip_sfc_clk_get_rate(sfc));
        }
  
        rockchip_sfc_adjust_op_work((struct spi_mem_op *)op);

diff --cc drivers/spi/spi-zynq-qspi.c
Simple merge