ASoC: SOF: amd: Fix for incorrect acp error register offsets
authorVijendar Mukunda <Vijendar.Mukunda@amd.com>
Tue, 13 Aug 2024 10:59:44 +0000 (16:29 +0530)
committerMark Brown <broonie@kernel.org>
Tue, 13 Aug 2024 11:39:19 +0000 (12:39 +0100)
Addition of 'dsp_intr_base' to ACP error register offsets points to
wrong register offsets in irq handler. Correct the acp error register
offsets. ACP error status register offset and acp error reason register
offset got changed from ACP6.0 onwards. Add 'acp_error_stat' and
'acp_sw0_i2s_err_reason' as descriptor fields in sof_amd_acp_desc
structure and update the values based on the ACP variant.
>From Rembrandt platform onwards, errors related to SW1 Soundwire manager
instance/I2S controller connected on P1 power tile is reported with
ACP_SW1_I2S_ERROR_REASON register. Add conditional check for the same.

Fixes: 96eb81851012 ("ASoC: SOF: amd: add interrupt handling for SoundWire manager devices")
Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
Link: https://patch.msgid.link/20240813105944.3126903-2-Vijendar.Mukunda@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>
sound/soc/sof/amd/acp-dsp-offset.h
sound/soc/sof/amd/acp.c
sound/soc/sof/amd/acp.h
sound/soc/sof/amd/pci-acp63.c
sound/soc/sof/amd/pci-rmb.c
sound/soc/sof/amd/pci-rn.c

index 59afbe2e0f42059f6d84429bcb601c59d8af0566..072b703f9b3f328626d867ac0f780b39203ec268 100644 (file)
 #define DSP_SW_INTR_CNTL_OFFSET                        0x0
 #define DSP_SW_INTR_STAT_OFFSET                        0x4
 #define DSP_SW_INTR_TRIG_OFFSET                        0x8
-#define ACP_ERROR_STATUS                       0x18C4
+#define ACP3X_ERROR_STATUS                     0x18C4
+#define ACP6X_ERROR_STATUS                     0x1A4C
 #define ACP3X_AXI2DAGB_SEM_0                   0x1880
 #define ACP5X_AXI2DAGB_SEM_0                   0x1884
 #define ACP6X_AXI2DAGB_SEM_0                   0x1874
 
 /* ACP common registers to report errors related to I2S & SoundWire interfaces */
-#define ACP_SW0_I2S_ERROR_REASON               0x18B4
+#define ACP3X_SW_I2S_ERROR_REASON              0x18C8
+#define ACP6X_SW0_I2S_ERROR_REASON             0x18B4
 #define ACP_SW1_I2S_ERROR_REASON               0x1A50
 
 /* Registers from ACP_SHA block */
index 9123427fab4e3046ff706bc4eb114bc22d12972f..d95f865669a699a704b28aa7768420febe3f97e7 100644 (file)
@@ -92,6 +92,7 @@ static int config_dma_channel(struct acp_dev_data *adata, unsigned int ch,
                              unsigned int idx, unsigned int dscr_count)
 {
        struct snd_sof_dev *sdev = adata->dev;
+       const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
        unsigned int val, status;
        int ret;
 
@@ -102,7 +103,7 @@ static int config_dma_channel(struct acp_dev_data *adata, unsigned int ch,
                                            val & (1 << ch), ACP_REG_POLL_INTERVAL,
                                            ACP_REG_POLL_TIMEOUT_US);
        if (ret < 0) {
-               status = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_ERROR_STATUS);
+               status = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->acp_error_stat);
                val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DMA_ERR_STS_0 + ch * sizeof(u32));
 
                dev_err(sdev->dev, "ACP_DMA_ERR_STS :0x%x ACP_ERROR_STATUS :0x%x\n", val, status);
@@ -402,9 +403,11 @@ static irqreturn_t acp_irq_handler(int irq, void *dev_id)
 
        if (val & ACP_ERROR_IRQ_MASK) {
                snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat, ACP_ERROR_IRQ_MASK);
-               snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + ACP_SW0_I2S_ERROR_REASON, 0);
-               snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + ACP_SW1_I2S_ERROR_REASON, 0);
-               snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + ACP_ERROR_STATUS, 0);
+               snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_sw0_i2s_err_reason, 0);
+               /* ACP_SW1_I2S_ERROR_REASON is newly added register from rmb platform onwards */
+               if (desc->rev >= 6)
+                       snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SW1_I2S_ERROR_REASON, 0);
+               snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_error_stat, 0);
                irq_flag = 1;
        }
 
index 87e79d500865a8e8e3314bbc3fe3015d42c82397..1af86b5b28db8074c66aa5d80072030f7e991cbf 100644 (file)
@@ -203,6 +203,8 @@ struct sof_amd_acp_desc {
        u32 probe_reg_offset;
        u32 reg_start_addr;
        u32 reg_end_addr;
+       u32 acp_error_stat;
+       u32 acp_sw0_i2s_err_reason;
        u32 sdw_max_link_count;
        u64 sdw_acpi_dev_addr;
 };
index fc8984447365718410b4320e8cd05fbf3802d804..986f5928caedd85fdc761ad2a14f23fefdda6323 100644 (file)
@@ -35,6 +35,8 @@ static const struct sof_amd_acp_desc acp63_chip_info = {
        .ext_intr_cntl = ACP6X_EXTERNAL_INTR_CNTL,
        .ext_intr_stat  = ACP6X_EXT_INTR_STAT,
        .ext_intr_stat1 = ACP6X_EXT_INTR_STAT1,
+       .acp_error_stat = ACP6X_ERROR_STATUS,
+       .acp_sw0_i2s_err_reason = ACP6X_SW0_I2S_ERROR_REASON,
        .dsp_intr_base  = ACP6X_DSP_SW_INTR_BASE,
        .sram_pte_offset = ACP6X_SRAM_PTE_OFFSET,
        .hw_semaphore_offset = ACP6X_AXI2DAGB_SEM_0,
index 4bc30951f8b0d711fc8baa6afa285a16a6ad330c..a366f904e6f31fa28197d0b62ba073e394bba698 100644 (file)
@@ -33,6 +33,8 @@ static const struct sof_amd_acp_desc rembrandt_chip_info = {
        .pgfsm_base     = ACP6X_PGFSM_BASE,
        .ext_intr_stat  = ACP6X_EXT_INTR_STAT,
        .dsp_intr_base  = ACP6X_DSP_SW_INTR_BASE,
+       .acp_error_stat = ACP6X_ERROR_STATUS,
+       .acp_sw0_i2s_err_reason = ACP6X_SW0_I2S_ERROR_REASON,
        .sram_pte_offset = ACP6X_SRAM_PTE_OFFSET,
        .hw_semaphore_offset = ACP6X_AXI2DAGB_SEM_0,
        .fusion_dsp_offset = ACP6X_DSP_FUSION_RUNSTALL,
index e08875bdfa8b16f3fcd1512223b5c351a735db21..2b7c53470ce82326f655a59da483553a34f3c7ed 100644 (file)
@@ -33,6 +33,8 @@ static const struct sof_amd_acp_desc renoir_chip_info = {
        .pgfsm_base     = ACP3X_PGFSM_BASE,
        .ext_intr_stat  = ACP3X_EXT_INTR_STAT,
        .dsp_intr_base  = ACP3X_DSP_SW_INTR_BASE,
+       .acp_error_stat = ACP3X_ERROR_STATUS,
+       .acp_sw0_i2s_err_reason = ACP3X_SW_I2S_ERROR_REASON,
        .sram_pte_offset = ACP3X_SRAM_PTE_OFFSET,
        .hw_semaphore_offset = ACP3X_AXI2DAGB_SEM_0,
        .acp_clkmux_sel = ACP3X_CLKMUX_SEL,