x86/mce: Check whether writes to MCA_STATUS are getting ignored

The platform can sometimes - depending on its settings - cause writes
to MCA_STATUS MSRs to get ignored, regardless of HWCR[McStatusWrEn]'s
value.

For further info see

  PPR for AMD Family 19h, Model 01h, Revision B1 Processors, doc ID 55898

at https://bugzilla.kernel.org/show_bug.cgi?id=206537.

Therefore, probe for ignored writes to MCA_STATUS to determine if hardware
error injection is at all possible.

  [ bp: Heavily massage commit message and patch. ]

Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lore.kernel.org/r/20220214233640.70510-2-Smita.KoralahalliChannabasappa@amd.com

diff --git a/arch/x86/kernel/cpu/mce/inject.c b/arch/x86/kernel/cpu/mce/inject.c
index 5fbd7ffb32334dc0097e5eede469cabcf3f060f4..12cf2e7ca33cc45765c3370bf1ded405d3d23f50 100644 (file)
--- a/arch/x86/kernel/cpu/mce/inject.c
+++ b/arch/x86/kernel/cpu/mce/inject.c
@@ -33,6 +33,8 @@
 
 #include "internal.h"
 
+static bool hw_injection_possible = true;
+
 /*
  * Collect all the MCi_XXX settings
  */
@@ -339,6 +341,8 @@ static int __set_inj(const char *buf)
 
        for (i = 0; i < N_INJ_TYPES; i++) {
                if (!strncmp(flags_options[i], buf, strlen(flags_options[i]))) {
+                       if (i > SW_INJ && !hw_injection_possible)
+                               continue;
                        inj_type = i;
                        return 0;
                }
@@ -717,11 +721,54 @@ static void __init debugfs_init(void)
                                    &i_mce, dfs_fls[i].fops);
 }
 
+static void check_hw_inj_possible(void)
+{
+       int cpu;
+       u8 bank;
+
+       /*
+        * This behavior exists only on SMCA systems though its not directly
+        * related to SMCA.
+        */
+       if (!cpu_feature_enabled(X86_FEATURE_SMCA))
+               return;
+
+       cpu = get_cpu();
+
+       for (bank = 0; bank < MAX_NR_BANKS; ++bank) {
+               u64 status = MCI_STATUS_VAL, ipid;
+
+               /* Check whether bank is populated */
+               rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), ipid);
+               if (!ipid)
+                       continue;
+
+               toggle_hw_mce_inject(cpu, true);
+
+               wrmsrl_safe(mca_msr_reg(bank, MCA_STATUS), status);
+               rdmsrl_safe(mca_msr_reg(bank, MCA_STATUS), &status);
+
+               if (!status) {
+                       hw_injection_possible = false;
+                       pr_warn("Platform does not allow *hardware* error injection."
+                               "Try using APEI EINJ instead.\n");
+               }
+
+               toggle_hw_mce_inject(cpu, false);
+
+               break;
+       }
+
+       put_cpu();
+}
+
 static int __init inject_init(void)
 {
        if (!alloc_cpumask_var(&mce_inject_cpumask, GFP_KERNEL))
                return -ENOMEM;
 
+       check_hw_inj_possible();
+
        debugfs_init();
 
        register_nmi_handler(NMI_LOCAL, mce_raise_notify, 0, "mce_notify");

diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/internal.h
index 4ae0e603f7fa895c01b2081210237752e5fdb668..7e03f5b7f6bd7d32641ef5ef083f1dcd33bc7733 100644 (file)
--- a/arch/x86/kernel/cpu/mce/internal.h
+++ b/arch/x86/kernel/cpu/mce/internal.h
@@ -211,7 +211,7 @@ noinstr u64 mce_rdmsrl(u32 msr);
 
 static __always_inline u32 mca_msr_reg(int bank, enum mca_msr reg)
 {
-       if (mce_flags.smca) {
+       if (cpu_feature_enabled(X86_FEATURE_SMCA)) {
                switch (reg) {
                case MCA_CTL:    return MSR_AMD64_SMCA_MCx_CTL(bank);
                case MCA_ADDR:   return MSR_AMD64_SMCA_MCx_ADDR(bank);