arm64: dts: ti: k3-j721s2: Fix clock IDs for MCSPI instances
authorAnurag Dutta <a-dutta@ti.com>
Wed, 23 Oct 2024 10:45:31 +0000 (16:15 +0530)
committerVignesh Raghavendra <vigneshr@ti.com>
Mon, 28 Oct 2024 15:20:40 +0000 (20:50 +0530)
The clock IDs for multiple MCSPI instances across wakeup domain
in J721s2 are incorrect when compared with documentation [1]. Fix the
clock IDs to their appropriate values.

[1]https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j721s2/clocks.html

Fixes: 04d7cb647b85 ("arm64: dts: ti: k3-j721s2: Add MCSPI nodes")

Signed-off-by: Anurag Dutta <a-dutta@ti.com>
Link: https://lore.kernel.org/r/20241023104532.3438851-4-a-dutta@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi

index 9889144d665a832e5346e13daa7887c9c968fbcd..92bf48fdbeba45ecca8c854db5f72fd3666239c5 100644 (file)
                #address-cells = <1>;
                #size-cells = <0>;
                power-domains = <&k3_pds 339 TI_SCI_PD_EXCLUSIVE>;
-               clocks = <&k3_clks 339 1>;
+               clocks = <&k3_clks 339 2>;
                status = "disabled";
        };
 
                #address-cells = <1>;
                #size-cells = <0>;
                power-domains = <&k3_pds 340 TI_SCI_PD_EXCLUSIVE>;
-               clocks = <&k3_clks 340 1>;
+               clocks = <&k3_clks 340 2>;
                status = "disabled";
        };
 
                #address-cells = <1>;
                #size-cells = <0>;
                power-domains = <&k3_pds 341 TI_SCI_PD_EXCLUSIVE>;
-               clocks = <&k3_clks 341 1>;
+               clocks = <&k3_clks 341 2>;
                status = "disabled";
        };
 
                #address-cells = <1>;
                #size-cells = <0>;
                power-domains = <&k3_pds 342 TI_SCI_PD_EXCLUSIVE>;
-               clocks = <&k3_clks 342 1>;
+               clocks = <&k3_clks 342 2>;
                status = "disabled";
        };
 
                #address-cells = <1>;
                #size-cells = <0>;
                power-domains = <&k3_pds 343 TI_SCI_PD_EXCLUSIVE>;
-               clocks = <&k3_clks 343 1>;
+               clocks = <&k3_clks 343 2>;
                status = "disabled";
        };
 
                #address-cells = <1>;
                #size-cells = <0>;
                power-domains = <&k3_pds 344 TI_SCI_PD_EXCLUSIVE>;
-               clocks = <&k3_clks 344 1>;
+               clocks = <&k3_clks 344 2>;
                status = "disabled";
        };
 
                #address-cells = <1>;
                #size-cells = <0>;
                power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>;
-               clocks = <&k3_clks 345 1>;
+               clocks = <&k3_clks 345 2>;
                status = "disabled";
        };
 
                #address-cells = <1>;
                #size-cells = <0>;
                power-domains = <&k3_pds 346 TI_SCI_PD_EXCLUSIVE>;
-               clocks = <&k3_clks 346 1>;
+               clocks = <&k3_clks 346 2>;
                status = "disabled";
        };
 
index c36888c455316774a07d69326262465ac958a6fc..bc31266126d0849c9baeda4b914400ae6ad5f244 100644 (file)
                #address-cells = <1>;
                #size-cells = <0>;
                power-domains = <&k3_pds 347 TI_SCI_PD_EXCLUSIVE>;
-               clocks = <&k3_clks 347 0>;
+               clocks = <&k3_clks 347 2>;
                status = "disabled";
        };
 
                #address-cells = <1>;
                #size-cells = <0>;
                power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>;
-               clocks = <&k3_clks 348 0>;
+               clocks = <&k3_clks 348 2>;
                status = "disabled";
        };
 
                #address-cells = <1>;
                #size-cells = <0>;
                power-domains = <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>;
-               clocks = <&k3_clks 349 0>;
+               clocks = <&k3_clks 349 2>;
                status = "disabled";
        };