drm/amd/amdgpu: apply command submission parser for JPEG v2+

This patch extends the same cs parser from JPEG v4.0.3 to
other JPEG versions (v2 and above).

Rename to more common name as jpeg_v2_dec_ring_parse_cs()
from jpeg_v4_0_3_dec_ring_parse_cs().

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: David (Ming Qiang) Wu <David.Wu3@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
index 98aa3ccd0d20244cc95a61cc0b854d7d12d46f79..41c0f8750dc1dbb5132d66e443a8aeb1d7d3c6d3 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
@@ -23,6 +23,7 @@
 
 #include "amdgpu.h"
 #include "amdgpu_jpeg.h"
+#include "amdgpu_cs.h"
 #include "amdgpu_pm.h"
 #include "soc15.h"
 #include "soc15d.h"
@@ -538,7 +539,11 @@ void jpeg_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
 
        amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET,
                0, 0, PACKETJ_TYPE0));
-       amdgpu_ring_write(ring, (vmid | (vmid << 4) | (vmid << 8)));
+
+       if (ring->funcs->parse_cs)
+               amdgpu_ring_write(ring, 0);
+       else
+               amdgpu_ring_write(ring, (vmid | (vmid << 4) | (vmid << 8)));
 
        amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET,
                0, 0, PACKETJ_TYPE0));
@@ -764,6 +769,7 @@ static const struct amdgpu_ring_funcs jpeg_v2_0_dec_ring_vm_funcs = {
        .get_rptr = jpeg_v2_0_dec_ring_get_rptr,
        .get_wptr = jpeg_v2_0_dec_ring_get_wptr,
        .set_wptr = jpeg_v2_0_dec_ring_set_wptr,
+       .parse_cs = jpeg_v2_dec_ring_parse_cs,
        .emit_frame_size =
                SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
                SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
@@ -810,3 +816,58 @@ const struct amdgpu_ip_block_version jpeg_v2_0_ip_block = {
                .rev = 0,
                .funcs = &jpeg_v2_0_ip_funcs,
 };
+
+/**
+ * jpeg_v2_dec_ring_parse_cs - command submission parser
+ *
+ * @parser: Command submission parser context
+ * @job: the job to parse
+ * @ib: the IB to parse
+ *
+ * Parse the command stream, return -EINVAL for invalid packet,
+ * 0 otherwise
+ */
+int jpeg_v2_dec_ring_parse_cs(struct amdgpu_cs_parser *parser,
+                             struct amdgpu_job *job,
+                             struct amdgpu_ib *ib)
+{
+       u32 i, reg, res, cond, type;
+       struct amdgpu_device *adev = parser->adev;
+
+       for (i = 0; i < ib->length_dw ; i += 2) {
+               reg  = CP_PACKETJ_GET_REG(ib->ptr[i]);
+               res  = CP_PACKETJ_GET_RES(ib->ptr[i]);
+               cond = CP_PACKETJ_GET_COND(ib->ptr[i]);
+               type = CP_PACKETJ_GET_TYPE(ib->ptr[i]);
+
+               if (res) /* only support 0 at the moment */
+                       return -EINVAL;
+
+               switch (type) {
+               case PACKETJ_TYPE0:
+                       if (cond != PACKETJ_CONDITION_CHECK0 || reg < JPEG_REG_RANGE_START ||
+                           reg > JPEG_REG_RANGE_END) {
+                               dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]);
+                               return -EINVAL;
+                       }
+                       break;
+               case PACKETJ_TYPE3:
+                       if (cond != PACKETJ_CONDITION_CHECK3 || reg < JPEG_REG_RANGE_START ||
+                           reg > JPEG_REG_RANGE_END) {
+                               dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]);
+                               return -EINVAL;
+                       }
+                       break;
+               case PACKETJ_TYPE6:
+                       if (ib->ptr[i] == CP_PACKETJ_NOP)
+                               continue;
+                       dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]);
+                       return -EINVAL;
+               default:
+                       dev_err(adev->dev, "Unknown packet type %d !\n", type);
+                       return -EINVAL;
+               }
+       }
+
+       return 0;
+}

diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h
index 654e43e83e2c43800974e6eba8e0de7aa0165304..63fadda7a673323b2edea79404d385ed4b9e131d 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h
@@ -45,6 +45,9 @@
 
 #define JRBC_DEC_EXTERNAL_REG_WRITE_ADDR                               0x18000
 
+#define JPEG_REG_RANGE_START                                           0x4000
+#define JPEG_REG_RANGE_END                                             0x41c2
+
 void jpeg_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring);
 void jpeg_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring);
 void jpeg_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
@@ -57,6 +60,9 @@ void jpeg_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
                                unsigned vmid, uint64_t pd_addr);
 void jpeg_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
 void jpeg_v2_0_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count);
+int jpeg_v2_dec_ring_parse_cs(struct amdgpu_cs_parser *parser,
+                             struct amdgpu_job *job,
+                             struct amdgpu_ib *ib);
 
 extern const struct amdgpu_ip_block_version jpeg_v2_0_ip_block;
 

diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
index d8ef95c847c2a7f2e85e3b6f247db8c41fc4d667..eedb9a829d9500d767ba4ee9bf5a5215a0cb1140 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
@@ -662,6 +662,7 @@ static const struct amdgpu_ring_funcs jpeg_v2_5_dec_ring_vm_funcs = {
        .get_rptr = jpeg_v2_5_dec_ring_get_rptr,
        .get_wptr = jpeg_v2_5_dec_ring_get_wptr,
        .set_wptr = jpeg_v2_5_dec_ring_set_wptr,
+       .parse_cs = jpeg_v2_dec_ring_parse_cs,
        .emit_frame_size =
                SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
                SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
@@ -691,6 +692,7 @@ static const struct amdgpu_ring_funcs jpeg_v2_6_dec_ring_vm_funcs = {
        .get_rptr = jpeg_v2_5_dec_ring_get_rptr,
        .get_wptr = jpeg_v2_5_dec_ring_get_wptr,
        .set_wptr = jpeg_v2_5_dec_ring_set_wptr,
+       .parse_cs = jpeg_v2_dec_ring_parse_cs,
        .emit_frame_size =
                SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
                SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +

diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
index 31cfa3ce6528d8fe7bb53a2caf2e09731c77a5ca..b1e7fd25afbcb935f1ac9a446d6775121f8f2628 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
@@ -560,6 +560,7 @@ static const struct amdgpu_ring_funcs jpeg_v3_0_dec_ring_vm_funcs = {
        .get_rptr = jpeg_v3_0_dec_ring_get_rptr,
        .get_wptr = jpeg_v3_0_dec_ring_get_wptr,
        .set_wptr = jpeg_v3_0_dec_ring_set_wptr,
+       .parse_cs = jpeg_v2_dec_ring_parse_cs,
        .emit_frame_size =
                SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
                SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +

diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
index 3dac8f259d7fb55e467b64985e27a92800fe6c14..6c5c1a68a9b7b80be7cf939714822746d2a5565d 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
@@ -727,6 +727,7 @@ static const struct amdgpu_ring_funcs jpeg_v4_0_dec_ring_vm_funcs = {
        .get_rptr = jpeg_v4_0_dec_ring_get_rptr,
        .get_wptr = jpeg_v4_0_dec_ring_get_wptr,
        .set_wptr = jpeg_v4_0_dec_ring_set_wptr,
+       .parse_cs = jpeg_v2_dec_ring_parse_cs,
        .emit_frame_size =
                SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
                SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +

diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.h b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.h
index 07d36c2abd6bb91d0541dcacbf03af16a99477e8..47638fd4d4e212b7e97d0a97f2b22e256b724d69 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.h
@@ -32,5 +32,4 @@ enum amdgpu_jpeg_v4_0_sub_block {
 };
 
 extern const struct amdgpu_ip_block_version jpeg_v4_0_ip_block;
-
 #endif /* __JPEG_V4_0_H__ */

diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
index a4ebceaaa09cdd313980fa2159d5958522a9db84..86958cb2c2ab2ba37aa2fb05e3c84d78480dd05d 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
@@ -23,9 +23,9 @@
 
 #include "amdgpu.h"
 #include "amdgpu_jpeg.h"
-#include "amdgpu_cs.h"
 #include "soc15.h"
 #include "soc15d.h"
+#include "jpeg_v2_0.h"
 #include "jpeg_v4_0_3.h"
 #include "mmsch_v4_0_3.h"
 
@@ -1083,7 +1083,7 @@ static const struct amdgpu_ring_funcs jpeg_v4_0_3_dec_ring_vm_funcs = {
        .get_rptr = jpeg_v4_0_3_dec_ring_get_rptr,
        .get_wptr = jpeg_v4_0_3_dec_ring_get_wptr,
        .set_wptr = jpeg_v4_0_3_dec_ring_set_wptr,
-       .parse_cs = jpeg_v4_0_3_dec_ring_parse_cs,
+       .parse_cs = jpeg_v2_dec_ring_parse_cs,
        .emit_frame_size =
                SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
                SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
@@ -1248,56 +1248,3 @@ static void jpeg_v4_0_3_set_ras_funcs(struct amdgpu_device *adev)
 {
        adev->jpeg.ras = &jpeg_v4_0_3_ras;
 }
-
-/**
- * jpeg_v4_0_3_dec_ring_parse_cs - command submission parser
- *
- * @parser: Command submission parser context
- * @job: the job to parse
- * @ib: the IB to parse
- *
- * Parse the command stream, return -EINVAL for invalid packet,
- * 0 otherwise
- */
-int jpeg_v4_0_3_dec_ring_parse_cs(struct amdgpu_cs_parser *parser,
-                            struct amdgpu_job *job,
-                            struct amdgpu_ib *ib)
-{
-       uint32_t i, reg, res, cond, type;
-       struct amdgpu_device *adev = parser->adev;
-
-       for (i = 0; i < ib->length_dw ; i += 2) {
-               reg  = CP_PACKETJ_GET_REG(ib->ptr[i]);
-               res  = CP_PACKETJ_GET_RES(ib->ptr[i]);
-               cond = CP_PACKETJ_GET_COND(ib->ptr[i]);
-               type = CP_PACKETJ_GET_TYPE(ib->ptr[i]);
-
-               if (res) /* only support 0 at the moment */
-                       return -EINVAL;
-
-               switch (type) {
-               case PACKETJ_TYPE0:
-                       if (cond != PACKETJ_CONDITION_CHECK0 || reg < JPEG_REG_RANGE_START || reg > JPEG_REG_RANGE_END) {
-                               dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]);
-                               return -EINVAL;
-                       }
-                       break;
-               case PACKETJ_TYPE3:
-                       if (cond != PACKETJ_CONDITION_CHECK3 || reg < JPEG_REG_RANGE_START || reg > JPEG_REG_RANGE_END) {
-                               dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]);
-                               return -EINVAL;
-                       }
-                       break;
-               case PACKETJ_TYPE6:
-                       if (ib->ptr[i] == CP_PACKETJ_NOP)
-                               continue;
-                       dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]);
-                       return -EINVAL;
-               default:
-                       dev_err(adev->dev, "Unknown packet type %d !\n", type);
-                       return -EINVAL;
-               }
-       }
-
-       return 0;
-}

diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.h b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.h
index 71c54b294e157e060e54307bcfbda336d93a484b..747a3e5f68564c381ecca77c13bfa08a5eb31f7c 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.h
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.h
@@ -46,9 +46,6 @@
 
 #define JRBC_DEC_EXTERNAL_REG_WRITE_ADDR                               0x18000
 
-#define JPEG_REG_RANGE_START                                           0x4000
-#define JPEG_REG_RANGE_END                                             0x41c2
-
 extern const struct amdgpu_ip_block_version jpeg_v4_0_3_ip_block;
 
 void jpeg_v4_0_3_dec_ring_emit_ib(struct amdgpu_ring *ring,
@@ -65,7 +62,5 @@ void jpeg_v4_0_3_dec_ring_insert_end(struct amdgpu_ring *ring);
 void jpeg_v4_0_3_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
 void jpeg_v4_0_3_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
                                        uint32_t val, uint32_t mask);
-int jpeg_v4_0_3_dec_ring_parse_cs(struct amdgpu_cs_parser *parser,
-                                 struct amdgpu_job *job,
-                                 struct amdgpu_ib *ib);
+
 #endif /* __JPEG_V4_0_3_H__ */

diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
index f96ac6bce526d3490f6451c495152576b7180237..44eeed445ea917a75b1f45fd40fbafc1e2fde2be 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
@@ -768,6 +768,7 @@ static const struct amdgpu_ring_funcs jpeg_v4_0_5_dec_ring_vm_funcs = {
        .get_rptr = jpeg_v4_0_5_dec_ring_get_rptr,
        .get_wptr = jpeg_v4_0_5_dec_ring_get_wptr,
        .set_wptr = jpeg_v4_0_5_dec_ring_set_wptr,
+       .parse_cs = jpeg_v2_dec_ring_parse_cs,
        .emit_frame_size =
                SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
                SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +

diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
index f4daff90c7709daa16b5b5ece2adcf56892e0a3c..d662aa841f97184376a73af57005bc32432557fe 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
@@ -26,6 +26,7 @@
 #include "amdgpu_pm.h"
 #include "soc15.h"
 #include "soc15d.h"
+#include "jpeg_v2_0.h"
 #include "jpeg_v4_0_3.h"
 
 #include "vcn/vcn_5_0_0_offset.h"
@@ -646,7 +647,7 @@ static const struct amdgpu_ring_funcs jpeg_v5_0_0_dec_ring_vm_funcs = {
        .get_rptr = jpeg_v5_0_0_dec_ring_get_rptr,
        .get_wptr = jpeg_v5_0_0_dec_ring_get_wptr,
        .set_wptr = jpeg_v5_0_0_dec_ring_set_wptr,
-       .parse_cs = jpeg_v4_0_3_dec_ring_parse_cs,
+       .parse_cs = jpeg_v2_dec_ring_parse_cs,
        .emit_frame_size =
                SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
                SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +