Define individual arrays to describe the register offsets. In this way
we can describe different IP variants that share the same register offsets
but have differences in other characteristics. Commit prepares for the
addition of fast mode plus.
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
};
struct riic_of_data {
- u8 regs[RIIC_REG_END];
+ const u8 *regs;
};
struct riic_dev {
pm_runtime_dont_use_autosuspend(dev);
}
+static const u8 riic_rz_a_regs[RIIC_REG_END] = {
+ [RIIC_ICCR1] = 0x00,
+ [RIIC_ICCR2] = 0x04,
+ [RIIC_ICMR1] = 0x08,
+ [RIIC_ICMR3] = 0x10,
+ [RIIC_ICSER] = 0x18,
+ [RIIC_ICIER] = 0x1c,
+ [RIIC_ICSR2] = 0x24,
+ [RIIC_ICBRL] = 0x34,
+ [RIIC_ICBRH] = 0x38,
+ [RIIC_ICDRT] = 0x3c,
+ [RIIC_ICDRR] = 0x40,
+};
+
static const struct riic_of_data riic_rz_a_info = {
- .regs = {
- [RIIC_ICCR1] = 0x00,
- [RIIC_ICCR2] = 0x04,
- [RIIC_ICMR1] = 0x08,
- [RIIC_ICMR3] = 0x10,
- [RIIC_ICSER] = 0x18,
- [RIIC_ICIER] = 0x1c,
- [RIIC_ICSR2] = 0x24,
- [RIIC_ICBRL] = 0x34,
- [RIIC_ICBRH] = 0x38,
- [RIIC_ICDRT] = 0x3c,
- [RIIC_ICDRR] = 0x40,
- },
+ .regs = riic_rz_a_regs,
+};
+
+static const u8 riic_rz_v2h_regs[RIIC_REG_END] = {
+ [RIIC_ICCR1] = 0x00,
+ [RIIC_ICCR2] = 0x01,
+ [RIIC_ICMR1] = 0x02,
+ [RIIC_ICMR3] = 0x04,
+ [RIIC_ICSER] = 0x06,
+ [RIIC_ICIER] = 0x07,
+ [RIIC_ICSR2] = 0x09,
+ [RIIC_ICBRL] = 0x10,
+ [RIIC_ICBRH] = 0x11,
+ [RIIC_ICDRT] = 0x12,
+ [RIIC_ICDRR] = 0x13,
};
static const struct riic_of_data riic_rz_v2h_info = {
- .regs = {
- [RIIC_ICCR1] = 0x00,
- [RIIC_ICCR2] = 0x01,
- [RIIC_ICMR1] = 0x02,
- [RIIC_ICMR3] = 0x04,
- [RIIC_ICSER] = 0x06,
- [RIIC_ICIER] = 0x07,
- [RIIC_ICSR2] = 0x09,
- [RIIC_ICBRL] = 0x10,
- [RIIC_ICBRH] = 0x11,
- [RIIC_ICDRT] = 0x12,
- [RIIC_ICDRR] = 0x13,
- },
+ .regs = riic_rz_v2h_regs,
};
static int riic_i2c_suspend(struct device *dev)