Merge tag 'Wimplicit-fallthrough-5.3-rc2' of git://git.kernel.org/pub/scm/linux/kerne...

Pull Wimplicit-fallthrough enablement from Gustavo A. R. Silva:
 "This marks switch cases where we are expecting to fall through, and
  globally enables the -Wimplicit-fallthrough option in the main
  Makefile.

  Finally, some missing-break fixes that have been tagged for -stable:

   - drm/amdkfd: Fix missing break in switch statement

   - drm/amdgpu/gfx10: Fix missing break in switch statement

  With these changes, we completely get rid of all the fall-through
  warnings in the kernel"

* tag 'Wimplicit-fallthrough-5.3-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/gustavoars/linux:
  Makefile: Globally enable fall-through warning
  drm/i915: Mark expected switch fall-throughs
  drm/amd/display: Mark expected switch fall-throughs
  drm/amdkfd/kfd_mqd_manager_v10: Avoid fall-through warning
  drm/amdgpu/gfx10: Fix missing break in switch statement
  drm/amdkfd: Fix missing break in switch statement
  perf/x86/intel: Mark expected switch fall-throughs
  mtd: onenand_base: Mark expected switch fall-through
  afs: fsclient: Mark expected switch fall-throughs
  afs: yfsclient: Mark expected switch fall-throughs
  can: mark expected switch fall-throughs
  firewire: mark expected switch fall-throughs

diff --combined drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 3df50c9c2fb0b82dd204fcb96c18fa66b1295121,35e8e29139b17de5b1a0b1ddb5b42b277f73bf7b..32773b7523d204a8b29266931fb4a9e577c571a4
--- 1/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
--- 2/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@@ -1441,15 -1441,6 +1441,15 @@@ static void gfx_v10_0_init_compute_vmid
        }
        nv_grbm_select(adev, 0, 0, 0, 0);
        mutex_unlock(&adev->srbm_mutex);
 +
 +      /* Initialize all compute VMIDs to have no GDS, GWS, or OA
 +         acccess. These should be enabled by FW for target VMIDs. */
 +      for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
 +              WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
 +              WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
 +              WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
 +              WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
 +      }
  }
  
  static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
@@@ -4620,6 -4611,7 +4620,7 @@@ gfx_v10_0_set_gfx_eop_interrupt_state(s
                cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
                                            TIME_STAMP_INT_ENABLE, 0);
                WREG32(cp_int_cntl_reg, cp_int_cntl);
+               break;
        case AMDGPU_IRQ_STATE_ENABLE:
                cp_int_cntl = RREG32(cp_int_cntl_reg);
                cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,