drm/tegra: nvdec: Fix TRANSCFG register offset

NVDEC's TRANSCFG register is at a different offset than VIC.
This becomes a problem now when context isolation is enabled and
the reset value of the register is no longer sufficient.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/drivers/gpu/drm/tegra/nvdec.c b/drivers/gpu/drm/tegra/nvdec.c
index 79e1e88203cf43a9e6929c622e8f5c3e6af12a5d..386f9b2e78c41fc30b6e683509b806c9c3f1ac9b 100644 (file)
--- a/drivers/gpu/drm/tegra/nvdec.c
+++ b/drivers/gpu/drm/tegra/nvdec.c
@@ -21,6 +21,8 @@
 #include "falcon.h"
 #include "vic.h"
 
+#define NVDEC_TFBIF_TRANSCFG                   0x2c44
+
 struct nvdec_config {
        const char *firmware;
        unsigned int version;
@@ -63,7 +65,7 @@ static int nvdec_boot(struct nvdec *nvdec)
                u32 value;
 
                value = TRANSCFG_ATT(1, TRANSCFG_SID_FALCON) | TRANSCFG_ATT(0, TRANSCFG_SID_HW);
-               nvdec_writel(nvdec, value, VIC_TFBIF_TRANSCFG);
+               nvdec_writel(nvdec, value, NVDEC_TFBIF_TRANSCFG);
 
                if (spec->num_ids > 0) {
                        value = spec->ids[0] & 0xffff;