dt-bindings: spi: spi-cadence: Describe power-domains property
authorMichal Simek <michal.simek@amd.com>
Thu, 3 Aug 2023 07:24:24 +0000 (09:24 +0200)
committerMark Brown <broonie@kernel.org>
Thu, 3 Aug 2023 16:07:10 +0000 (17:07 +0100)
ZynqMP Cadence SPI IP core has own power domain that's why describe it as
optional property.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/987430ee905fd299fe962663d94f848b341c87df.1691047461.git.michal.simek@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Documentation/devicetree/bindings/spi/spi-cadence.yaml

index b7552739b5545e0f19fdb580325344494a3122bf..9eda7f0d2869e3d461a17f3c4db6e65de42e423f 100644 (file)
@@ -49,6 +49,9 @@ properties:
     enum: [ 0, 1 ]
     default: 0
 
+  power-domains:
+    maxItems: 1
+
 required:
   - compatible
   - reg