drm/i915/display: Consider fractional vdsc bpp while computing m_n values
authorAnkit Nautiyal <ankit.k.nautiyal@intel.com>
Fri, 10 Nov 2023 10:10:12 +0000 (15:40 +0530)
committerAnkit Nautiyal <ankit.k.nautiyal@intel.com>
Tue, 14 Nov 2023 09:35:22 +0000 (15:05 +0530)
MTL+ supports fractional compressed bits_per_pixel, with precision of
1/16. This compressed bpp is stored in U6.4 format.
Accommodate this precision while computing m_n values.

v1:
Replace the computation of 'data_clock' with 'data_clock =
DIV_ROUND_UP(data_clock, 16).' (Sui Jingfeng).

v2:
Rebase and pass bits_per_pixel in U6.4 format.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Sui Jingfeng <suijingfeng@loongson.cn>
Link: https://patchwork.freedesktop.org/patch/msgid/20231110101020.4067342-4-ankit.k.nautiyal@intel.com
drivers/gpu/drm/i915/display/intel_display.c
drivers/gpu/drm/i915/display/intel_dp.c
drivers/gpu/drm/i915/display/intel_dp_mst.c
drivers/gpu/drm/i915/display/intel_fdi.c

index b4a8e3087e508c55beaafb660c9ab407ead13397..125903007a292812ebf9a4556a3949bc769ee92f 100644 (file)
@@ -2415,12 +2415,12 @@ add_bw_alloc_overhead(int link_clock, int bw_overhead,
 }
 
 void
-intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
+intel_link_compute_m_n(u16 bits_per_pixel_x16, int nlanes,
                       int pixel_clock, int link_clock,
                       int bw_overhead,
                       struct intel_link_m_n *m_n)
 {
-       u32 data_clock = bits_per_pixel * pixel_clock;
+       u32 data_clock = DIV_ROUND_UP(bits_per_pixel_x16 * pixel_clock, 16);
        u32 data_m;
        u32 data_n;
 
index e341e4b155c9ce0cf0845b90a52ab3e57a79631e..d4118d25f39bd70c4be3c242ccd9eb2b5dfbdf27 100644 (file)
@@ -2688,7 +2688,7 @@ static bool can_enable_drrs(struct intel_connector *connector,
 static void
 intel_dp_drrs_compute_config(struct intel_connector *connector,
                             struct intel_crtc_state *pipe_config,
-                            int link_bpp)
+                            int link_bpp_x16)
 {
        struct drm_i915_private *i915 = to_i915(connector->base.dev);
        const struct drm_display_mode *downclock_mode =
@@ -2713,7 +2713,7 @@ intel_dp_drrs_compute_config(struct intel_connector *connector,
        if (pipe_config->splitter.enable)
                pixel_clock /= pipe_config->splitter.link_count;
 
-       intel_link_compute_m_n(link_bpp, pipe_config->lane_count, pixel_clock,
+       intel_link_compute_m_n(link_bpp_x16, pipe_config->lane_count, pixel_clock,
                               pipe_config->port_clock,
                               intel_dp_bw_fec_overhead(pipe_config->fec_enable),
                               &pipe_config->dp_m2_n2);
@@ -2817,7 +2817,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
        struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
        const struct drm_display_mode *fixed_mode;
        struct intel_connector *connector = intel_dp->attached_connector;
-       int ret = 0, link_bpp;
+       int ret = 0, link_bpp_x16;
 
        if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A)
                pipe_config->has_pch_encoder = true;
@@ -2866,10 +2866,10 @@ intel_dp_compute_config(struct intel_encoder *encoder,
                drm_dp_enhanced_frame_cap(intel_dp->dpcd);
 
        if (pipe_config->dsc.compression_enable)
-               link_bpp = to_bpp_int(pipe_config->dsc.compressed_bpp_x16);
+               link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16;
        else
-               link_bpp = intel_dp_output_bpp(pipe_config->output_format,
-                                              pipe_config->pipe_bpp);
+               link_bpp_x16 = to_bpp_x16(intel_dp_output_bpp(pipe_config->output_format,
+                                                             pipe_config->pipe_bpp));
 
        if (intel_dp->mso_link_count) {
                int n = intel_dp->mso_link_count;
@@ -2893,7 +2893,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 
        intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
 
-       intel_link_compute_m_n(link_bpp,
+       intel_link_compute_m_n(link_bpp_x16,
                               pipe_config->lane_count,
                               adjusted_mode->crtc_clock,
                               pipe_config->port_clock,
@@ -2909,7 +2909,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 
        intel_vrr_compute_config(pipe_config, conn_state);
        intel_psr_compute_config(intel_dp, pipe_config, conn_state);
-       intel_dp_drrs_compute_config(connector, pipe_config, link_bpp);
+       intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16);
        intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
        intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
 
index 4db902dc6eb16ae5715ae76072363847b48f9384..0cb9405f59eaa14f2f659d688f59c281b1917ad6 100644 (file)
@@ -71,7 +71,7 @@ static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp
 
 static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state,
                                    const struct intel_connector *connector,
-                                   bool ssc, bool dsc, int bpp)
+                                   bool ssc, bool dsc, int bpp_x16)
 {
        const struct drm_display_mode *adjusted_mode =
                &crtc_state->hw.adjusted_mode;
@@ -95,7 +95,7 @@ static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state,
        overhead = drm_dp_bw_overhead(crtc_state->lane_count,
                                      adjusted_mode->hdisplay,
                                      dsc_slice_count,
-                                     to_bpp_x16(bpp),
+                                     bpp_x16,
                                      flags);
 
        /*
@@ -108,16 +108,16 @@ static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state,
 static void intel_dp_mst_compute_m_n(const struct intel_crtc_state *crtc_state,
                                     const struct intel_connector *connector,
                                     bool ssc, bool dsc,
-                                    int bpp,
+                                    int bpp_x16,
                                     struct intel_link_m_n *m_n)
 {
        const struct drm_display_mode *adjusted_mode =
                &crtc_state->hw.adjusted_mode;
        int overhead = intel_dp_mst_bw_overhead(crtc_state,
                                                connector,
-                                               ssc, dsc, bpp);
+                                               ssc, dsc, bpp_x16);
 
-       intel_link_compute_m_n(bpp, crtc_state->lane_count,
+       intel_link_compute_m_n(bpp_x16, crtc_state->lane_count,
                               adjusted_mode->crtc_clock,
                               crtc_state->port_clock,
                               overhead,
@@ -181,9 +181,9 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
                link_bpp = dsc ? bpp :
                        intel_dp_output_bpp(crtc_state->output_format, bpp);
 
-               intel_dp_mst_compute_m_n(crtc_state, connector, false, dsc, link_bpp,
+               intel_dp_mst_compute_m_n(crtc_state, connector, false, dsc, to_bpp_x16(link_bpp),
                                         &crtc_state->dp_m_n);
-               intel_dp_mst_compute_m_n(crtc_state, connector, true, dsc, link_bpp,
+               intel_dp_mst_compute_m_n(crtc_state, connector, true, dsc, to_bpp_x16(link_bpp),
                                         &remote_m_n);
 
                /*
index 1d87fbc1e81383dee16d5547ac266fc2d04423fa..295a0f24ebbf78754089de23b86e29de5e6d3021 100644 (file)
@@ -339,7 +339,8 @@ int ilk_fdi_compute_config(struct intel_crtc *crtc,
 
        pipe_config->fdi_lanes = lane;
 
-       intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
+       intel_link_compute_m_n(to_bpp_x16(pipe_config->pipe_bpp),
+                              lane, fdi_dotclock,
                               link_bw,
                               intel_dp_bw_fec_overhead(false),
                               &pipe_config->fdi_m_n);