arm64: dts: ti: am642-phyboard-electra: Add PRU-ICSSG nodes
authorWadim Egorov <w.egorov@phytec.de>
Thu, 15 Aug 2024 11:32:11 +0000 (13:32 +0200)
committerNishanth Menon <nm@ti.com>
Sat, 24 Aug 2024 19:42:06 +0000 (14:42 -0500)
The phyBOARD-Electra implements two Ethernet ports utilizing PRUs.
Add configuration for both mac ports & PHYs.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Link: https://lore.kernel.org/r/20240815113212.3720403-1-w.egorov@phytec.de
Signed-off-by: Nishanth Menon <nm@ti.com>
arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts

index 30729b49dd690dc6e61ae89d82452592e8ed7b11..60285d736e07a38e8458399ffe20a4981200522b 100644 (file)
@@ -28,6 +28,8 @@
        model = "PHYTEC phyBOARD-Electra-AM64x RDK";
 
        aliases {
+               ethernet1 = &icssg0_emac0;
+               ethernet2 = &icssg0_emac1;
                mmc1 = &sdhci1;
                serial2 = &main_uart0;
                serial3 = &main_uart1;
                standby-gpios = <&main_gpio0 35 GPIO_ACTIVE_HIGH>;
        };
 
+       /* Dual Ethernet application node on PRU-ICSSG0 */
+       ethernet {
+               compatible = "ti,am642-icssg-prueth";
+               pinctrl-names = "default";
+               pinctrl-0 = <&icssg0_rgmii1_pins_default>, <&icssg0_rgmii2_pins_default>;
+
+               interrupt-parent = <&icssg0_intc>;
+               interrupts = <24 0 2>, <25 1 3>;
+               interrupt-names = "tx_ts0", "tx_ts1";
+
+               sram = <&oc_sram>;
+               firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
+                               "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
+                               "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
+                               "ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
+                               "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
+                               "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
+
+               dmas = <&main_pktdma 0xc100 15>, /* egress slice 0 */
+                      <&main_pktdma 0xc101 15>, /* egress slice 0 */
+                      <&main_pktdma 0xc102 15>, /* egress slice 0 */
+                      <&main_pktdma 0xc103 15>, /* egress slice 0 */
+                      <&main_pktdma 0xc104 15>, /* egress slice 1 */
+                      <&main_pktdma 0xc105 15>, /* egress slice 1 */
+                      <&main_pktdma 0xc106 15>, /* egress slice 1 */
+                      <&main_pktdma 0xc107 15>, /* egress slice 1 */
+                      <&main_pktdma 0x4100 15>, /* ingress slice 0 */
+                      <&main_pktdma 0x4101 15>; /* ingress slice 1 */
+               dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
+                           "tx1-0", "tx1-1", "tx1-2", "tx1-3",
+                           "rx0", "rx1";
+
+               ti,prus = <&pru0_0>, <&rtu0_0>, <&tx_pru0_0>, <&pru0_1>, <&rtu0_1>, <&tx_pru0_1>;
+               ti,pruss-gp-mux-sel = <2>,      /* MII mode */
+                                     <2>,
+                                     <2>,
+                                     <2>,      /* MII mode */
+                                     <2>,
+                                     <2>;
+
+               ti,mii-g-rt = <&icssg0_mii_g_rt>;
+               ti,mii-rt = <&icssg0_mii_rt>;
+               ti,iep = <&icssg0_iep0>, <&icssg0_iep1>;
+
+               ethernet-ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       icssg0_emac0: port@0 {
+                               reg = <0>;
+                               phy-handle = <&icssg0_phy1>;
+                               phy-mode = "rgmii-id";
+                               /* Filled in by bootloader */
+                               local-mac-address = [00 00 00 00 00 00];
+                               ti,syscon-rgmii-delay = <&main_conf 0x4100>;
+                       };
+
+                       icssg0_emac1: port@1 {
+                               reg = <1>;
+                               phy-handle = <&icssg0_phy2>;
+                               phy-mode = "rgmii-id";
+                               /* Filled in by bootloader */
+                               local-mac-address = [00 00 00 00 00 00];
+                               ti,syscon-rgmii-delay = <&main_conf 0x4104>;
+                       };
+               };
+       };
+
        keys {
                compatible = "gpio-keys";
                autorepeat;
                >;
        };
 
+       clkout0_pins_default: clkout0-default-pins {
+               pinctrl-single,pins = <
+                       AM64X_IOPAD(0x0274, PIN_OUTPUT, 5)      /* (A19) EXT_REFCLK1.CLKOUT0 */
+               >;
+       };
+
        gpio_keys_pins_default: gpio-keys-default-pins {
                pinctrl-single,pins = <
                        AM64X_IOPAD(0x0044, PIN_INPUT, 7)       /* (T18) GPMC0_AD2.GPIO0_17 */
                >;
        };
 
+       icssg0_mdio_pins_default: icssg0-mdio-default-pins {
+               pinctrl-single,pins = <
+                       AM64X_IOPAD(0x0200, PIN_INPUT, 0)       /* (P2) PRG0_MDIO0_MDIO */
+                       AM64X_IOPAD(0x0204, PIN_OUTPUT, 0)      /* (P3) PRG0_MDIO0_MDC */
+                       AM64X_IOPAD(0x01A8, PIN_OUTPUT, 7)      /* (V1) PRG0_PRU0_GPO18.GPIO1_18 */
+                       AM64X_IOPAD(0x01AC, PIN_OUTPUT, 7)      /* (W1) PRG0_PRU0_GPO19.GPIO1_19 */
+               >;
+       };
+
+       icssg0_rgmii1_pins_default: icssg0-rgmii1-default-pins {
+               pinctrl-single,pins = <
+                       AM64X_IOPAD(0x0160, PIN_INPUT, 2)       /* (Y1) PRG0_PRU0_GPO0.PRG0_RGMII1_RD0 */
+                       AM64X_IOPAD(0x0164, PIN_INPUT, 2)       /* (R4) PRG0_PRU0_GPO1.PRG0_RGMII1_RD1 */
+                       AM64X_IOPAD(0x0168, PIN_INPUT, 2)       /* (U2) PRG0_PRU0_GPO2.PRG0_RGMII1_RD2 */
+                       AM64X_IOPAD(0x016c, PIN_INPUT, 2)       /* (V2) PRG0_PRU0_GPO3.PRG0_RGMII1_RD3 */
+                       AM64X_IOPAD(0x0170, PIN_INPUT, 2)       /* (AA2) PRG0_PRU0_GPO4.PRG0_RGMII1_RX_CTL */
+                       AM64X_IOPAD(0x0178, PIN_INPUT, 2)       /* (T3) PRG0_PRU0_GPO6.PRG0_RGMII1_RXC */
+                       AM64X_IOPAD(0x018c, PIN_OUTPUT, 2)      /* (Y3) PRG0_PRU0_GPO11.PRG0_RGMII1_TD0 */
+                       AM64X_IOPAD(0x0190, PIN_OUTPUT, 2)      /* (AA3) PRG0_PRU0_GPO12.PRG0_RGMII1_TD1 */
+                       AM64X_IOPAD(0x0194, PIN_OUTPUT, 2)      /* (R6) PRG0_PRU0_GPO13.PRG0_RGMII1_TD2 */
+                       AM64X_IOPAD(0x0198, PIN_OUTPUT, 2)      /* (V4) PRG0_PRU0_GPO14.PRG0_RGMII1_TD3 */
+                       AM64X_IOPAD(0x019c, PIN_OUTPUT, 2)      /* (T5) PRG0_PRU0_GPO15.PRG0_RGMII1_TX_CTL */
+                       AM64X_IOPAD(0x01a0, PIN_OUTPUT, 2)      /* (U4) PRG0_PRU0_GPO16.PRG0_RGMII1_TXC */
+               >;
+       };
+
+       icssg0_rgmii2_pins_default: icssg0-rgmii2-default-pins {
+               pinctrl-single,pins = <
+                       AM64X_IOPAD(0x01b0, PIN_INPUT, 2)       /* (Y2) PRG0_PRU1_GPO0.PRG0_RGMII2_RD0 */
+                       AM64X_IOPAD(0x01b4, PIN_INPUT, 2)       /* (W2) PRG0_PRU1_GPO1.PRG0_RGMII2_RD1 */
+                       AM64X_IOPAD(0x01b8, PIN_INPUT, 2)       /* (V3) PRG0_PRU1_GPO2.PRG0_RGMII2_RD2 */
+                       AM64X_IOPAD(0x01bc, PIN_INPUT, 2)       /* (T4) PRG0_PRU1_GPO3.PRG0_RGMII2_RD3 */
+                       AM64X_IOPAD(0x01c0, PIN_INPUT, 2)       /* (W3) PRG0_PRU1_GPO4.PRG0_RGMII2_RX_CTL */
+                       AM64X_IOPAD(0x01c8, PIN_INPUT, 2)       /* (R5) PRG0_PRU1_GPO6.PRG0_RGMII2_RXC */
+                       AM64X_IOPAD(0x01dc, PIN_OUTPUT, 2)      /* (W4) PRG0_PRU1_GPO11.PRG0_RGMII2_TD0 */
+                       AM64X_IOPAD(0x01e0, PIN_OUTPUT, 2)      /* (Y4) PRG0_PRU1_GPO12.PRG0_RGMII2_TD1 */
+                       AM64X_IOPAD(0x01e4, PIN_OUTPUT, 2)      /* (T6) PRG0_PRU1_GPO13.PRG0_RGMII2_TD2 */
+                       AM64X_IOPAD(0x01e8, PIN_OUTPUT, 2)      /* (U6) PRG0_PRU1_GPO14.PRG0_RGMII2_TD3 */
+                       AM64X_IOPAD(0x01ec, PIN_OUTPUT, 2)      /* (U5) PRG0_PRU1_GPO15.PRG0_RGMII2_TX_CTL */
+                       AM64X_IOPAD(0x01f0, PIN_OUTPUT, 2)      /* (AA4) PRG0_PRU1_GPO16.PRG0_RGMII2_TXC */
+               >;
+       };
+
        main_i2c1_pins_default: main-i2c1-default-pins {
                pinctrl-single,pins = <
                        AM64X_IOPAD(0x0268, PIN_INPUT, 0)       /* (C18) I2C1_SCL */
        };
 };
 
+&icssg0_mdio {
+       pinctrl-names = "default";
+       pinctrl-0 = <&icssg0_mdio_pins_default &clkout0_pins_default>;
+       status = "okay";
+
+       icssg0_phy1: ethernet-phy@1 {
+               compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22";
+               reg = <0x1>;
+               tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+               rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+               reset-gpios = <&main_gpio1 18 GPIO_ACTIVE_LOW>;
+               reset-assert-us = <1000>;
+               reset-deassert-us = <1000>;
+               ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+       };
+
+       icssg0_phy2: ethernet-phy@2 {
+               compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22";
+               reg = <0x2>;
+               tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+               rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+               reset-gpios = <&main_gpio1 19 GPIO_ACTIVE_LOW>;
+               reset-assert-us = <1000>;
+               reset-deassert-us = <1000>;
+               ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+       };
+};
+
 &main_i2c1 {
        status = "okay";
        pinctrl-names = "default";