drm/nouveau/gr/gk104-: move rop_active_fbps init to nonctx
authorBen Skeggs <bskeggs@redhat.com>
Tue, 19 Apr 2016 01:10:38 +0000 (11:10 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Fri, 20 May 2016 04:43:04 +0000 (14:43 +1000)
Matches newer RM.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
15 files changed:
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c

index e01aa1ac9ab59d38cce17837778f1bed1982c856..ac895edce164558fff1893405aef32f5cbf486ff 100644 (file)
@@ -81,8 +81,6 @@ void gk104_grctx_generate_bundle(struct gf100_grctx *);
 void gk104_grctx_generate_pagepool(struct gf100_grctx *);
 void gk104_grctx_generate_unkn(struct gf100_gr *);
 void gk104_grctx_generate_r418bb8(struct gf100_gr *);
-void gk104_grctx_generate_rop_active_fbps(struct gf100_gr *);
-
 
 void gm107_grctx_generate_bundle(struct gf100_grctx *);
 void gm107_grctx_generate_pagepool(struct gf100_grctx *);
index 0c99f3c3a376bb8fb0682fd4b404228fc32d7656..9ba337778ef550ac0d7ab270f8f8f32105dba54b 100644 (file)
@@ -942,15 +942,6 @@ gk104_grctx_generate_r418bb8(struct gf100_gr *gr)
                nvkm_wr32(device, 0x40780c + (i * 4), data[i]);
 }
 
-void
-gk104_grctx_generate_rop_active_fbps(struct gf100_gr *gr)
-{
-       struct nvkm_device *device = gr->base.engine.subdev.device;
-       const u32 fbp_count = nvkm_rd32(device, 0x120074);
-       nvkm_mask(device, 0x408850, 0x0000000f, fbp_count); /* zrop */
-       nvkm_mask(device, 0x408958, 0x0000000f, fbp_count); /* crop */
-}
-
 void
 gk104_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
 {
@@ -983,7 +974,6 @@ gk104_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
                nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000);
 
        nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr);
-       gk104_grctx_generate_rop_active_fbps(gr);
        nvkm_mask(device, 0x419f78, 0x00000001, 0x00000000);
 
        gf100_gr_icmd(gr, grctx->icmd);
index 7625d6f73e8a166b7a059ae3edfc6a9f1c3f0a27..da7c35a6a3d20dadc5766860197801c887541303 100644 (file)
@@ -52,8 +52,6 @@ gk20a_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
 
        nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr);
 
-       gk104_grctx_generate_rop_active_fbps(gr);
-
        nvkm_mask(device, 0x5044b0, 0x08000000, 0x08000000);
 
        gf100_gr_wait_idle(gr);
index e77fb3d290d80d9afeaf151138325799192a365b..053ff2f850b90565e4e18f12981b03adc66cb5bc 100644 (file)
@@ -985,8 +985,6 @@ gm107_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
 
        nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr);
 
-       gk104_grctx_generate_rop_active_fbps(gr);
-
        gf100_gr_icmd(gr, grctx->icmd);
        nvkm_wr32(device, 0x404154, idle_timeout);
        gf100_gr_mthd(gr, grctx->mthd);
index e65b70a01a88695fb6f6eae7200b5f9dfa613908..db209d33f48648e307be0d3c5fa3e6e156c62fbf 100644 (file)
@@ -45,15 +45,6 @@ gm200_grctx_generate_tpcid(struct gf100_gr *gr)
        }
 }
 
-static void
-gm200_grctx_generate_rop_active_fbps(struct gf100_gr *gr)
-{
-       struct nvkm_device *device = gr->base.engine.subdev.device;
-       const u32 fbp_count = nvkm_rd32(device, 0x12006c);
-       nvkm_mask(device, 0x408850, 0x0000000f, fbp_count); /* zrop */
-       nvkm_mask(device, 0x408958, 0x0000000f, fbp_count); /* crop */
-}
-
 void
 gm200_grctx_generate_405b60(struct gf100_gr *gr)
 {
@@ -113,8 +104,6 @@ gm200_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
 
        nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr);
 
-       gm200_grctx_generate_rop_active_fbps(gr);
-
        for (tmp = 0, i = 0; i < gr->gpc_nr; i++)
                tmp |= ((1 << gr->tpc_nr[i]) - 1) << (i * 4);
        nvkm_wr32(device, 0x4041c4, tmp);
index ba30d94a2ffc56eb3bf7c7f0f01497ff4c8524f5..e5702e3e0a5aa1f97c75576d77530085d55256b6 100644 (file)
@@ -62,7 +62,6 @@ gm20b_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
 
        nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr);
 
-       gk104_grctx_generate_rop_active_fbps(gr);
        nvkm_wr32(device, 0x408908, nvkm_rd32(device, 0x410108) | 0x80000000);
 
        for (tmp = 0, i = 0; i < gr->gpc_nr; i++)
index 90c70e777dffb142a500cf0a74be31294fd6857b..611888c0dbacf21a4825bffe86530b07bf24067a 100644 (file)
@@ -119,6 +119,7 @@ struct gf100_gr_func {
        void (*dtor)(struct gf100_gr *);
        int (*init)(struct gf100_gr *);
        void (*init_gpc_mmu)(struct gf100_gr *);
+       void (*init_rop_active_fbps)(struct gf100_gr *);
        void (*set_hww_esr_report_mask)(struct gf100_gr *);
        const struct gf100_gr_pack *mmio;
        struct {
@@ -137,6 +138,7 @@ int gf100_gr_init(struct gf100_gr *);
 int gf100_gr_rops(struct gf100_gr *);
 
 int gk104_gr_init(struct gf100_gr *);
+void gk104_gr_init_rop_active_fbps(struct gf100_gr *);
 
 int gk20a_gr_init(struct gf100_gr *);
 
index 2aebae4df2fda06b5569925a5856d16965b3139d..c6a3f6d8a8ca3aa8fadda1f28a30eaf1d8dff8b3 100644 (file)
@@ -179,6 +179,15 @@ gk104_gr_pack_mmio[] = {
  * PGRAPH engine/subdev functions
  ******************************************************************************/
 
+void
+gk104_gr_init_rop_active_fbps(struct gf100_gr *gr)
+{
+       struct nvkm_device *device = gr->base.engine.subdev.device;
+       const u32 fbp_count = nvkm_rd32(device, 0x120074);
+       nvkm_mask(device, 0x408850, 0x0000000f, fbp_count); /* zrop */
+       nvkm_mask(device, 0x408958, 0x0000000f, fbp_count); /* crop */
+}
+
 int
 gk104_gr_init(struct gf100_gr *gr)
 {
@@ -230,6 +239,8 @@ gk104_gr_init(struct gf100_gr *gr)
        nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918);
        nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800));
 
+       gr->func->init_rop_active_fbps(gr);
+
        nvkm_wr32(device, 0x400500, 0x00010001);
 
        nvkm_wr32(device, 0x400100, 0xffffffff);
@@ -312,6 +323,7 @@ gk104_gr_gpccs_ucode = {
 static const struct gf100_gr_func
 gk104_gr = {
        .init = gk104_gr_init,
+       .init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
        .mmio = gk104_gr_pack_mmio,
        .fecs.ucode = &gk104_gr_fecs_ucode,
        .gpccs.ucode = &gk104_gr_gpccs_ucode,
index de1685c625c30b2f19d0a8dacf28449f9b9d47ea..f18af897410330bedc8d90fe06d1068b59e9f627 100644 (file)
@@ -183,6 +183,7 @@ gk110_gr_gpccs_ucode = {
 static const struct gf100_gr_func
 gk110_gr = {
        .init = gk104_gr_init,
+       .init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
        .mmio = gk110_gr_pack_mmio,
        .fecs.ucode = &gk110_gr_fecs_ucode,
        .gpccs.ucode = &gk110_gr_gpccs_ucode,
index f5f53e6c03e3739418a51d8d35445ec79f566bf8..2f029cad40cd04b343e5de2b0318542d3847e66e 100644 (file)
@@ -103,6 +103,7 @@ gk110b_gr_pack_mmio[] = {
 static const struct gf100_gr_func
 gk110b_gr = {
        .init = gk104_gr_init,
+       .init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
        .mmio = gk110b_gr_pack_mmio,
        .fecs.ucode = &gk110_gr_fecs_ucode,
        .gpccs.ucode = &gk110_gr_gpccs_ucode,
index ca66e9e62650c9064eece2651dbc393da695cd0f..01eb0e8cd4d594a05e8da93f060c328f6c0ccf41 100644 (file)
@@ -162,6 +162,7 @@ gk208_gr_gpccs_ucode = {
 static const struct gf100_gr_func
 gk208_gr = {
        .init = gk104_gr_init,
+       .init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
        .mmio = gk208_gr_pack_mmio,
        .fecs.ucode = &gk208_gr_fecs_ucode,
        .gpccs.ucode = &gk208_gr_gpccs_ucode,
index 62f40b9aaec75cbd24f0147f715124ea2f911018..4ca8ed15191c6ea158ef1bf8ef1cb6ed4a770661 100644 (file)
@@ -272,6 +272,8 @@ gk20a_gr_init(struct gf100_gr *gr)
 
        nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918);
 
+       gr->func->init_rop_active_fbps(gr);
+
        /* Enable FIFO access */
        nvkm_wr32(device, 0x400500, 0x00010001);
 
@@ -309,6 +311,7 @@ gk20a_gr_init(struct gf100_gr *gr)
 static const struct gf100_gr_func
 gk20a_gr = {
        .init = gk20a_gr_init,
+       .init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
        .set_hww_esr_report_mask = gk20a_gr_set_hww_esr_report_mask,
        .rops = gf100_gr_rops,
        .ppc_nr = 1,
index 487bd65b167d80ff0ece39c0da3fdacb5e7abb31..56b9669f076aed732f8580e08d28524cda7c2ae2 100644 (file)
@@ -358,6 +358,8 @@ gm107_gr_init(struct gf100_gr *gr)
        nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918);
        nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800));
 
+       gr->func->init_rop_active_fbps(gr);
+
        nvkm_wr32(device, 0x400500, 0x00010001);
 
        nvkm_wr32(device, 0x400100, 0xffffffff);
@@ -440,6 +442,7 @@ gm107_gr_gpccs_ucode = {
 static const struct gf100_gr_func
 gm107_gr = {
        .init = gm107_gr_init,
+       .init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
        .mmio = gm107_gr_pack_mmio,
        .fecs.ucode = &gm107_gr_fecs_ucode,
        .gpccs.ucode = &gm107_gr_gpccs_ucode,
index 28002a606ac8838b26cdf5d8c9e70fb44380888a..d9f320fa7dce36f65d5c645027ac643c006e94c9 100644 (file)
@@ -52,6 +52,15 @@ gm200_gr_init_gpc_mmu(struct gf100_gr *gr)
        nvkm_wr32(device, 0x4188b0, nvkm_rd32(device, 0x100cc4));
 }
 
+static void
+gm200_gr_init_rop_active_fbps(struct gf100_gr *gr)
+{
+       struct nvkm_device *device = gr->base.engine.subdev.device;
+       const u32 fbp_count = nvkm_rd32(device, 0x12006c);
+       nvkm_mask(device, 0x408850, 0x0000000f, fbp_count); /* zrop */
+       nvkm_mask(device, 0x408958, 0x0000000f, fbp_count); /* crop */
+}
+
 int
 gm200_gr_init(struct gf100_gr *gr)
 {
@@ -98,6 +107,8 @@ gm200_gr_init(struct gf100_gr *gr)
        nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800));
        nvkm_wr32(device, GPC_BCAST(0x033c), nvkm_rd32(device, 0x100804));
 
+       gr->func->init_rop_active_fbps(gr);
+
        nvkm_wr32(device, 0x400500, 0x00010001);
        nvkm_wr32(device, 0x400100, 0xffffffff);
        nvkm_wr32(device, 0x40013c, 0xffffffff);
@@ -199,6 +210,7 @@ static const struct gf100_gr_func
 gm200_gr = {
        .init = gm200_gr_init,
        .init_gpc_mmu = gm200_gr_init_gpc_mmu,
+       .init_rop_active_fbps = gm200_gr_init_rop_active_fbps,
        .rops = gm200_gr_rops,
        .ppc_nr = 2,
        .grctx = &gm200_grctx,
index 712f036d09f3a3e8792f9aa6cbbd8084bbdd9476..69479af1d829fa5ae0625a29daf3bf68be97d1ed 100644 (file)
@@ -66,6 +66,7 @@ static const struct gf100_gr_func
 gm20b_gr = {
        .init = gk20a_gr_init,
        .init_gpc_mmu = gm20b_gr_init_gpc_mmu,
+       .init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
        .set_hww_esr_report_mask = gm20b_gr_set_hww_esr_report_mask,
        .rops = gm200_gr_rops,
        .ppc_nr = 1,