staging: clocking-wizard: Update the fixed factor divisors

Update the fixed factor clock registration to register the divisors.

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Link: https://lore.kernel.org/r/1614172241-17326-4-git-send-email-shubhrajyoti.datta@xilinx.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c b/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c
index 57f80ba8416bc15c46d33bc57ec5f8b86a821a23..9cc2f6d0751ad24332ceb67a692a868e9a23e3ac 100644 (file)
--- a/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c
+++ b/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c
@@ -135,8 +135,10 @@ static int clk_wzrd_probe(struct platform_device *pdev)
        u32 reg;
        unsigned long rate;
        const char *clk_name;
+       void __iomem *ctrl_reg;
        struct clk_wzrd *clk_wzrd;
        struct device_node *np = pdev->dev.of_node;
+       unsigned long flags = 0;
 
        clk_wzrd = devm_kzalloc(&pdev->dev, sizeof(*clk_wzrd), GFP_KERNEL);
        if (!clk_wzrd)
@@ -198,6 +200,7 @@ static int clk_wzrd_probe(struct platform_device *pdev)
                ret = -ENOMEM;
                goto err_disable_clk;
        }
+
        clk_wzrd->clks_internal[wzrd_clk_mul] = clk_register_fixed_factor
                        (&pdev->dev, clk_name,
                         __clk_get_name(clk_wzrd->clk_in1),
@@ -209,19 +212,19 @@ static int clk_wzrd_probe(struct platform_device *pdev)
                goto err_disable_clk;
        }
 
-       /* register div */
-       reg = (readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0)) &
-                       WZRD_DIVCLK_DIVIDE_MASK) >> WZRD_DIVCLK_DIVIDE_SHIFT;
        clk_name = kasprintf(GFP_KERNEL, "%s_mul_div", dev_name(&pdev->dev));
        if (!clk_name) {
                ret = -ENOMEM;
                goto err_rm_int_clk;
        }
 
-       clk_wzrd->clks_internal[wzrd_clk_mul_div] = clk_register_fixed_factor
+       ctrl_reg = clk_wzrd->base + WZRD_CLK_CFG_REG(0);
+       /* register div */
+       clk_wzrd->clks_internal[wzrd_clk_mul_div] = clk_register_divider
                        (&pdev->dev, clk_name,
                         __clk_get_name(clk_wzrd->clks_internal[wzrd_clk_mul]),
-                        0, 1, reg);
+                       flags, ctrl_reg, 0, 8, CLK_DIVIDER_ONE_BASED |
+                       CLK_DIVIDER_ALLOW_ZERO, &clkwzrd_lock);
        if (IS_ERR(clk_wzrd->clks_internal[wzrd_clk_mul_div])) {
                dev_err(&pdev->dev, "unable to register divider clock\n");
                ret = PTR_ERR(clk_wzrd->clks_internal[wzrd_clk_mul_div]);