perf->max_per_pipe_ib = 0;
perf->core_clk_rate = 0;
} else if (core_perf->perf_tune.mode == DPU_PERF_MODE_FIXED) {
- perf->bw_ctl = core_perf->fix_core_ab_vote;
+ perf->bw_ctl = core_perf->fix_core_ab_vote * 1000ULL;
perf->max_per_pipe_ib = core_perf->fix_core_ib_vote;
perf->core_clk_rate = core_perf->fix_core_clk_rate;
} else {
&perf->fix_core_clk_rate);
debugfs_create_u32("fix_core_ib_vote", 0600, entry,
&perf->fix_core_ib_vote);
- debugfs_create_u64("fix_core_ab_vote", 0600, entry,
+ debugfs_create_u32("fix_core_ab_vote", 0600, entry,
&perf->fix_core_ab_vote);
return 0;
* @enable_bw_release: debug control for bandwidth release
* @fix_core_clk_rate: fixed core clock request in Hz used in mode 2
* @fix_core_ib_vote: fixed core ib vote in KBps used in mode 2
- * @fix_core_ab_vote: fixed core ab vote in bps used in mode 2
+ * @fix_core_ab_vote: fixed core ab vote in KBps used in mode 2
*/
struct dpu_core_perf {
const struct dpu_perf_cfg *perf_cfg;
u32 enable_bw_release;
u64 fix_core_clk_rate;
u32 fix_core_ib_vote;
- u64 fix_core_ab_vote;
+ u32 fix_core_ab_vote;
};
int dpu_core_perf_crtc_check(struct drm_crtc *crtc,