powerpc/dt_cpu_ftrs: Add MMA feature

Matrix multiple assist (MMA) is a new feature added to ISAv3.1 and
POWER10. Support on powernv can be selected via a firmware CPU device
tree feature which enables it via a PCR bit.

Signed-off-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200521014341.29095-7-alistair@popple.id.au

diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index dd20af367b57a404dbb2740d1527a3666d4710a1..88e6c78100d9bfc1fe21ae77ac470ba532b1ce6a 100644 (file)
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -481,7 +481,8 @@
 #define   PCR_VEC_DIS  (__MASK(63-0))  /* Vec. disable (bit NA since POWER8) */
 #define   PCR_VSX_DIS  (__MASK(63-1))  /* VSX disable (bit NA since POWER8) */
 #define   PCR_TM_DIS   (__MASK(63-2))  /* Trans. memory disable (POWER8) */
-#define   PCR_HIGH_BITS        (PCR_VEC_DIS | PCR_VSX_DIS | PCR_TM_DIS)
+#define   PCR_MMA_DIS  (__MASK(63-3)) /* Matrix-Multiply Accelerator */
+#define   PCR_HIGH_BITS        (PCR_MMA_DIS | PCR_VEC_DIS | PCR_VSX_DIS | PCR_TM_DIS)
 /*
  * These bits are used in the function kvmppc_set_arch_compat() to specify and
  * determine both the compatibility level which we want to emulate and the

diff --git a/arch/powerpc/kernel/dt_cpu_ftrs.c b/arch/powerpc/kernel/dt_cpu_ftrs.c
index 87a5d47415eb363adf5d8d6a152482c0b0bc1a58..3a409517c031dc9506e649b9f9b7c3eca7322434 100644 (file)
--- a/arch/powerpc/kernel/dt_cpu_ftrs.c
+++ b/arch/powerpc/kernel/dt_cpu_ftrs.c
@@ -75,6 +75,7 @@ static struct {
        u64     lpcr_clear;
        u64     hfscr;
        u64     fscr;
+       u64     pcr;
 } system_registers;
 
 static void (*init_pmu_registers)(void);
@@ -102,7 +103,7 @@ static void __restore_cpu_cpufeatures(void)
        if (hv_mode) {
                mtspr(SPRN_LPID, 0);
                mtspr(SPRN_HFSCR, system_registers.hfscr);
-               mtspr(SPRN_PCR, PCR_MASK);
+               mtspr(SPRN_PCR, system_registers.pcr);
        }
        mtspr(SPRN_FSCR, system_registers.fscr);
 
@@ -561,6 +562,18 @@ static int __init feat_enable_large_ci(struct dt_cpu_feature *f)
        return 1;
 }
 
+static int __init feat_enable_mma(struct dt_cpu_feature *f)
+{
+       u64 pcr;
+
+       feat_enable(f);
+       pcr = mfspr(SPRN_PCR);
+       pcr &= ~PCR_MMA_DIS;
+       mtspr(SPRN_PCR, pcr);
+
+       return 1;
+}
+
 struct dt_cpu_feature_match {
        const char *name;
        int (*enable)(struct dt_cpu_feature *f);
@@ -635,6 +648,7 @@ static struct dt_cpu_feature_match __initdata
        {"vector-binary16", feat_enable, 0},
        {"wait-v3", feat_enable, 0},
        {"prefix-instructions", feat_enable, 0},
+       {"matrix-multiply-assist", feat_enable_mma, 0},
 };
 
 static bool __initdata using_dt_cpu_ftrs;
@@ -785,6 +799,7 @@ static void __init cpufeatures_setup_finished(void)
        system_registers.lpcr = mfspr(SPRN_LPCR);
        system_registers.hfscr = mfspr(SPRN_HFSCR);
        system_registers.fscr = mfspr(SPRN_FSCR);
+       system_registers.pcr = mfspr(SPRN_PCR);
 
        pr_info("final cpu/mmu features = 0x%016lx 0x%08x\n",
                cur_cpu_spec->cpu_features, cur_cpu_spec->mmu_features);