arm64: dts: ti: k3-j784s4-mcu-wakeup: Add FSS OSPI0 and FSS OSPI1

TI K3 J784S4 has the Cadence OSPI controllers OSPI0 and OSPI1 on FSS
bus for interfacing with OSPI flashes. Add the nodes to allow using
SPI flashes.

Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Link: https://lore.kernel.org/r/20230504080305.38986-2-a-nandan@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
index d640e31a83351f30861bb941ff2ec62e0a2adb1e..ae9a8856bc402a85109496e9cb5720f510229666 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
@@ -430,4 +430,45 @@
                        compatible = "ti,am3359-adc";
                };
        };
+
+       fss: bus@47000000 {
+               compatible = "simple-bus";
+               reg = <0x00 0x47000000 0x00 0x100>;
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               ospi0: spi@47040000 {
+                       compatible = "ti,am654-ospi", "cdns,qspi-nor";
+                       reg = <0x00 0x47040000 0x00 0x100>,
+                             <0x05 0x0000000 0x01 0x0000000>;
+                       interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
+                       cdns,fifo-depth = <256>;
+                       cdns,fifo-width = <4>;
+                       cdns,trigger-address = <0x0>;
+                       clocks = <&k3_clks 161 7>;
+                       assigned-clocks = <&k3_clks 161 7>;
+                       assigned-clock-parents = <&k3_clks 161 9>;
+                       assigned-clock-rates = <166666666>;
+                       power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               ospi1: spi@47050000 {
+                       compatible = "ti,am654-ospi", "cdns,qspi-nor";
+                       reg = <0x00 0x47050000 0x00 0x100>,
+                             <0x07 0x0000000 0x01 0x0000000>;
+                       interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
+                       cdns,fifo-depth = <256>;
+                       cdns,fifo-width = <4>;
+                       cdns,trigger-address = <0x0>;
+                       clocks = <&k3_clks 162 7>;
+                       power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+       };
 };