counter: stm32-lptimer-cnt: fix error handling when enabling

In case the stm32_lptim_set_enable_state() fails to update CMP and ARR,
a timeout error is raised, by regmap_read_poll_timeout. It may happen,
when the lptimer runs on a slow clock, and the clock is gated only
few times during the polling.

Badly, when this happen, STM32_LPTIM_ENABLE in CR register has been set.
So the 'enable' state in sysfs wrongly lies on the counter being
correctly enabled, due to CR is read as one in stm32_lptim_is_enabled().

To fix both issues:
- enable the clock before writing CMP, ARR and polling ISR bits. It will
avoid the possible timeout error.
- clear the ENABLE bit in CR and disable the clock in the error path.

Fixes: d8958824cf07 ("iio: counter: Add support for STM32 LPTimer")
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Link: https://lore.kernel.org/r/20250224170657.3368236-1-fabrice.gasnier@foss.st.com
Signed-off-by: William Breathitt Gray <wbg@kernel.org>

diff --git a/drivers/counter/stm32-lptimer-cnt.c b/drivers/counter/stm32-lptimer-cnt.c
index cf73f65baf606ce1cba820e1fc44a03fc72a3627..b249c8647639f731041ed1b30c12c35618d02db5 100644 (file)
--- a/drivers/counter/stm32-lptimer-cnt.c
+++ b/drivers/counter/stm32-lptimer-cnt.c
@@ -58,37 +58,43 @@ static int stm32_lptim_set_enable_state(struct stm32_lptim_cnt *priv,
                return 0;
        }
 
+       ret = clk_enable(priv->clk);
+       if (ret)
+               goto disable_cnt;
+
        /* LP timer must be enabled before writing CMP & ARR */
        ret = regmap_write(priv->regmap, STM32_LPTIM_ARR, priv->ceiling);
        if (ret)
-               return ret;
+               goto disable_clk;
 
        ret = regmap_write(priv->regmap, STM32_LPTIM_CMP, 0);
        if (ret)
-               return ret;
+               goto disable_clk;
 
        /* ensure CMP & ARR registers are properly written */
        ret = regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val,
                                       (val & STM32_LPTIM_CMPOK_ARROK) == STM32_LPTIM_CMPOK_ARROK,
                                       100, 1000);
        if (ret)
-               return ret;
+               goto disable_clk;
 
        ret = regmap_write(priv->regmap, STM32_LPTIM_ICR,
                           STM32_LPTIM_CMPOKCF_ARROKCF);
        if (ret)
-               return ret;
+               goto disable_clk;
 
-       ret = clk_enable(priv->clk);
-       if (ret) {
-               regmap_write(priv->regmap, STM32_LPTIM_CR, 0);
-               return ret;
-       }
        priv->enabled = true;
 
        /* Start LP timer in continuous mode */
        return regmap_update_bits(priv->regmap, STM32_LPTIM_CR,
                                  STM32_LPTIM_CNTSTRT, STM32_LPTIM_CNTSTRT);
+
+disable_clk:
+       clk_disable(priv->clk);
+disable_cnt:
+       regmap_write(priv->regmap, STM32_LPTIM_CR, 0);
+
+       return ret;
 }
 
 static int stm32_lptim_setup(struct stm32_lptim_cnt *priv, int enable)