drm/amdgpu: remove the queue manager
authorChristian König <christian.koenig@amd.com>
Mon, 16 Jul 2018 13:19:20 +0000 (15:19 +0200)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 27 Aug 2018 16:10:47 +0000 (11:10 -0500)
Not needed any more since that is now done by the scheduler.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/Makefile
drivers/gpu/drm/amd/amdgpu/amdgpu.h
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c [deleted file]

index 7d7faaf299efbcc2e5a38f3f593601336e809140..860cb8731c7cf4d9a8d79b4aa71bba5d76fdd3ae 100644 (file)
@@ -51,8 +51,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
        amdgpu_prime.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \
        amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o \
        amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_atomfirmware.o \
-       amdgpu_queue_mgr.o amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o \
-       amdgpu_ids.o
+       amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o
 
 # add asic specific block
 amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \
index 07924d41ee8936ced3e35bb486ed38d77c051b2c..20e81df5cd947d93625de1948e41a3b70adb0613 100644 (file)
@@ -477,29 +477,6 @@ struct amdgpu_ib {
 
 extern const struct drm_sched_backend_ops amdgpu_sched_ops;
 
-/*
- * Queue manager
- */
-struct amdgpu_queue_mapper {
-       int             hw_ip;
-       struct mutex    lock;
-       /* protected by lock */
-       struct amdgpu_ring *queue_map[AMDGPU_MAX_RINGS];
-};
-
-struct amdgpu_queue_mgr {
-       struct amdgpu_queue_mapper mapper[AMDGPU_MAX_IP_NUM];
-};
-
-int amdgpu_queue_mgr_init(struct amdgpu_device *adev,
-                         struct amdgpu_queue_mgr *mgr);
-int amdgpu_queue_mgr_fini(struct amdgpu_device *adev,
-                         struct amdgpu_queue_mgr *mgr);
-int amdgpu_queue_mgr_map(struct amdgpu_device *adev,
-                        struct amdgpu_queue_mgr *mgr,
-                        u32 hw_ip, u32 instance, u32 ring,
-                        struct amdgpu_ring **out_ring);
-
 /*
  * context related structures
  */
@@ -513,7 +490,6 @@ struct amdgpu_ctx_ring {
 struct amdgpu_ctx {
        struct kref             refcount;
        struct amdgpu_device    *adev;
-       struct amdgpu_queue_mgr queue_mgr;
        unsigned                reset_counter;
        unsigned        reset_counter_query;
        uint32_t                vram_lost_counter;
@@ -537,6 +513,9 @@ struct amdgpu_ctx_mgr {
 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
 int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
 
+int amdgpu_ctx_get_ring(struct amdgpu_ctx *ctx,
+                       u32 hw_ip, u32 instance, u32 ring,
+                       struct amdgpu_ring **out_ring);
 int amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
                              struct dma_fence *fence, uint64_t *seq);
 struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
index dc3b2f980d871a22bce6ac973b37c2bbff28a960..55667ab4fbf5c3046ff2849dc7300cf970d33938 100644 (file)
@@ -1008,8 +1008,9 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
                                return -EINVAL;
                }
 
-               r = amdgpu_queue_mgr_map(adev, &parser->ctx->queue_mgr, chunk_ib->ip_type,
-                                        chunk_ib->ip_instance, chunk_ib->ring, &ring);
+               r = amdgpu_ctx_get_ring(parser->ctx, chunk_ib->ip_type,
+                                       chunk_ib->ip_instance, chunk_ib->ring,
+                                       &ring);
                if (r)
                        return r;
 
@@ -1067,10 +1068,9 @@ static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p,
                if (ctx == NULL)
                        return -EINVAL;
 
-               r = amdgpu_queue_mgr_map(p->adev, &ctx->queue_mgr,
-                                        deps[i].ip_type,
-                                        deps[i].ip_instance,
-                                        deps[i].ring, &ring);
+               r = amdgpu_ctx_get_ring(ctx, deps[i].ip_type,
+                                       deps[i].ip_instance,
+                                       deps[i].ring, &ring);
                if (r) {
                        amdgpu_ctx_put(ctx);
                        return r;
@@ -1331,7 +1331,6 @@ int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
                         struct drm_file *filp)
 {
        union drm_amdgpu_wait_cs *wait = data;
-       struct amdgpu_device *adev = dev->dev_private;
        unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
        struct amdgpu_ring *ring = NULL;
        struct amdgpu_ctx *ctx;
@@ -1342,9 +1341,8 @@ int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
        if (ctx == NULL)
                return -EINVAL;
 
-       r = amdgpu_queue_mgr_map(adev, &ctx->queue_mgr,
-                                wait->in.ip_type, wait->in.ip_instance,
-                                wait->in.ring, &ring);
+       r = amdgpu_ctx_get_ring(ctx, wait->in.ip_type, wait->in.ip_instance,
+                               wait->in.ring, &ring);
        if (r) {
                amdgpu_ctx_put(ctx);
                return r;
@@ -1391,8 +1389,8 @@ static struct dma_fence *amdgpu_cs_get_fence(struct amdgpu_device *adev,
        if (ctx == NULL)
                return ERR_PTR(-EINVAL);
 
-       r = amdgpu_queue_mgr_map(adev, &ctx->queue_mgr, user->ip_type,
-                                user->ip_instance, user->ring, &ring);
+       r = amdgpu_ctx_get_ring(ctx, user->ip_type, user->ip_instance,
+                               user->ring, &ring);
        if (r) {
                amdgpu_ctx_put(ctx);
                return ERR_PTR(r);
index a078e68e031926e4c27021fd3246a0bc053b771a..e5acc72b05d2a2883a77c137aff4b31d001abd3c 100644 (file)
@@ -121,10 +121,6 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
                        goto failed;
        }
 
-       r = amdgpu_queue_mgr_init(adev, &ctx->queue_mgr);
-       if (r)
-               goto failed;
-
        return 0;
 
 failed:
@@ -150,13 +146,72 @@ static void amdgpu_ctx_fini(struct kref *ref)
        kfree(ctx->fences);
        ctx->fences = NULL;
 
-       amdgpu_queue_mgr_fini(adev, &ctx->queue_mgr);
-
        mutex_destroy(&ctx->lock);
 
        kfree(ctx);
 }
 
+int amdgpu_ctx_get_ring(struct amdgpu_ctx *ctx,
+                       u32 hw_ip, u32 instance, u32 ring,
+                       struct amdgpu_ring **out_ring)
+{
+       struct amdgpu_device *adev = ctx->adev;
+       unsigned num_rings = 0;
+
+       /* Right now all IPs have only one instance - multiple rings. */
+       if (instance != 0) {
+               DRM_DEBUG("invalid ip instance: %d\n", instance);
+               return -EINVAL;
+       }
+
+       switch (hw_ip) {
+       case AMDGPU_HW_IP_GFX:
+               *out_ring = &adev->gfx.gfx_ring[ring];
+               num_rings = adev->gfx.num_gfx_rings;
+               break;
+       case AMDGPU_HW_IP_COMPUTE:
+               *out_ring = &adev->gfx.compute_ring[ring];
+               num_rings = adev->gfx.num_compute_rings;
+               break;
+       case AMDGPU_HW_IP_DMA:
+               *out_ring = &adev->sdma.instance[ring].ring;
+               num_rings = adev->sdma.num_instances;
+               break;
+       case AMDGPU_HW_IP_UVD:
+               *out_ring = &adev->uvd.inst[0].ring;
+               num_rings = adev->uvd.num_uvd_inst;
+               break;
+       case AMDGPU_HW_IP_VCE:
+               *out_ring = &adev->vce.ring[ring];
+               num_rings = adev->vce.num_rings;
+               break;
+       case AMDGPU_HW_IP_UVD_ENC:
+               *out_ring = &adev->uvd.inst[0].ring_enc[ring];
+               num_rings = adev->uvd.num_enc_rings;
+               break;
+       case AMDGPU_HW_IP_VCN_DEC:
+               *out_ring = &adev->vcn.ring_dec;
+               num_rings = 1;
+               break;
+       case AMDGPU_HW_IP_VCN_ENC:
+               *out_ring = &adev->vcn.ring_enc[ring];
+               num_rings = adev->vcn.num_enc_rings;
+               break;
+       case AMDGPU_HW_IP_VCN_JPEG:
+               *out_ring = &adev->vcn.ring_jpeg;
+               num_rings = 1;
+               break;
+       default:
+               DRM_ERROR("unknown HW IP type: %d\n", hw_ip);
+               return -EINVAL;
+       }
+
+       if (ring > num_rings)
+               return -EINVAL;
+
+       return 0;
+}
+
 static int amdgpu_ctx_alloc(struct amdgpu_device *adev,
                            struct amdgpu_fpriv *fpriv,
                            struct drm_file *filp,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c
deleted file mode 100644 (file)
index a172bba..0000000
+++ /dev/null
@@ -1,316 +0,0 @@
-/*
- * Copyright 2017 Valve Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Andres Rodriguez
- */
-
-#include "amdgpu.h"
-#include "amdgpu_ring.h"
-
-static int amdgpu_queue_mapper_init(struct amdgpu_queue_mapper *mapper,
-                                   int hw_ip)
-{
-       if (!mapper)
-               return -EINVAL;
-
-       if (hw_ip > AMDGPU_MAX_IP_NUM)
-               return -EINVAL;
-
-       mapper->hw_ip = hw_ip;
-       mutex_init(&mapper->lock);
-
-       memset(mapper->queue_map, 0, sizeof(mapper->queue_map));
-
-       return 0;
-}
-
-static struct amdgpu_ring *amdgpu_get_cached_map(struct amdgpu_queue_mapper *mapper,
-                                         int ring)
-{
-       return mapper->queue_map[ring];
-}
-
-static int amdgpu_update_cached_map(struct amdgpu_queue_mapper *mapper,
-                            int ring, struct amdgpu_ring *pring)
-{
-       if (WARN_ON(mapper->queue_map[ring])) {
-               DRM_ERROR("Un-expected ring re-map\n");
-               return -EINVAL;
-       }
-
-       mapper->queue_map[ring] = pring;
-
-       return 0;
-}
-
-static int amdgpu_identity_map(struct amdgpu_device *adev,
-                              struct amdgpu_queue_mapper *mapper,
-                              u32 ring,
-                              struct amdgpu_ring **out_ring)
-{
-       switch (mapper->hw_ip) {
-       case AMDGPU_HW_IP_GFX:
-               *out_ring = &adev->gfx.gfx_ring[ring];
-               break;
-       case AMDGPU_HW_IP_COMPUTE:
-               *out_ring = &adev->gfx.compute_ring[ring];
-               break;
-       case AMDGPU_HW_IP_DMA:
-               *out_ring = &adev->sdma.instance[ring].ring;
-               break;
-       case AMDGPU_HW_IP_UVD:
-               *out_ring = &adev->uvd.inst[0].ring;
-               break;
-       case AMDGPU_HW_IP_VCE:
-               *out_ring = &adev->vce.ring[ring];
-               break;
-       case AMDGPU_HW_IP_UVD_ENC:
-               *out_ring = &adev->uvd.inst[0].ring_enc[ring];
-               break;
-       case AMDGPU_HW_IP_VCN_DEC:
-               *out_ring = &adev->vcn.ring_dec;
-               break;
-       case AMDGPU_HW_IP_VCN_ENC:
-               *out_ring = &adev->vcn.ring_enc[ring];
-               break;
-       case AMDGPU_HW_IP_VCN_JPEG:
-               *out_ring = &adev->vcn.ring_jpeg;
-               break;
-       default:
-               *out_ring = NULL;
-               DRM_ERROR("unknown HW IP type: %d\n", mapper->hw_ip);
-               return -EINVAL;
-       }
-
-       return amdgpu_update_cached_map(mapper, ring, *out_ring);
-}
-
-static enum amdgpu_ring_type amdgpu_hw_ip_to_ring_type(int hw_ip)
-{
-       switch (hw_ip) {
-       case AMDGPU_HW_IP_GFX:
-               return AMDGPU_RING_TYPE_GFX;
-       case AMDGPU_HW_IP_COMPUTE:
-               return AMDGPU_RING_TYPE_COMPUTE;
-       case AMDGPU_HW_IP_DMA:
-               return AMDGPU_RING_TYPE_SDMA;
-       case AMDGPU_HW_IP_UVD:
-               return AMDGPU_RING_TYPE_UVD;
-       case AMDGPU_HW_IP_VCE:
-               return AMDGPU_RING_TYPE_VCE;
-       default:
-               DRM_ERROR("Invalid HW IP specified %d\n", hw_ip);
-               return -1;
-       }
-}
-
-static int amdgpu_lru_map(struct amdgpu_device *adev,
-                         struct amdgpu_queue_mapper *mapper,
-                         u32 user_ring, bool lru_pipe_order,
-                         struct amdgpu_ring **out_ring)
-{
-       int r, i, j;
-       int ring_type = amdgpu_hw_ip_to_ring_type(mapper->hw_ip);
-       int ring_blacklist[AMDGPU_MAX_RINGS];
-       struct amdgpu_ring *ring;
-
-       /* 0 is a valid ring index, so initialize to -1 */
-       memset(ring_blacklist, 0xff, sizeof(ring_blacklist));
-
-       for (i = 0, j = 0; i < AMDGPU_MAX_RINGS; i++) {
-               ring = mapper->queue_map[i];
-               if (ring)
-                       ring_blacklist[j++] = ring->idx;
-       }
-
-       r = amdgpu_ring_lru_get(adev, ring_type, ring_blacklist,
-                               j, lru_pipe_order, out_ring);
-       if (r)
-               return r;
-
-       return amdgpu_update_cached_map(mapper, user_ring, *out_ring);
-}
-
-/**
- * amdgpu_queue_mgr_init - init an amdgpu_queue_mgr struct
- *
- * @adev: amdgpu_device pointer
- * @mgr: amdgpu_queue_mgr structure holding queue information
- *
- * Initialize the the selected @mgr (all asics).
- *
- * Returns 0 on success, error on failure.
- */
-int amdgpu_queue_mgr_init(struct amdgpu_device *adev,
-                         struct amdgpu_queue_mgr *mgr)
-{
-       int i, r;
-
-       if (!adev || !mgr)
-               return -EINVAL;
-
-       memset(mgr, 0, sizeof(*mgr));
-
-       for (i = 0; i < AMDGPU_MAX_IP_NUM; ++i) {
-               r = amdgpu_queue_mapper_init(&mgr->mapper[i], i);
-               if (r)
-                       return r;
-       }
-
-       return 0;
-}
-
-/**
- * amdgpu_queue_mgr_fini - de-initialize an amdgpu_queue_mgr struct
- *
- * @adev: amdgpu_device pointer
- * @mgr: amdgpu_queue_mgr structure holding queue information
- *
- * De-initialize the the selected @mgr (all asics).
- *
- * Returns 0 on success, error on failure.
- */
-int amdgpu_queue_mgr_fini(struct amdgpu_device *adev,
-                         struct amdgpu_queue_mgr *mgr)
-{
-       return 0;
-}
-
-/**
- * amdgpu_queue_mgr_map - Map a userspace ring id to an amdgpu_ring
- *
- * @adev: amdgpu_device pointer
- * @mgr: amdgpu_queue_mgr structure holding queue information
- * @hw_ip: HW IP enum
- * @instance: HW instance
- * @ring: user ring id
- * @our_ring: pointer to mapped amdgpu_ring
- *
- * Map a userspace ring id to an appropriate kernel ring. Different
- * policies are configurable at a HW IP level.
- *
- * Returns 0 on success, error on failure.
- */
-int amdgpu_queue_mgr_map(struct amdgpu_device *adev,
-                        struct amdgpu_queue_mgr *mgr,
-                        u32 hw_ip, u32 instance, u32 ring,
-                        struct amdgpu_ring **out_ring)
-{
-       int i, r, ip_num_rings = 0;
-       struct amdgpu_queue_mapper *mapper = &mgr->mapper[hw_ip];
-
-       if (!adev || !mgr || !out_ring)
-               return -EINVAL;
-
-       if (hw_ip >= AMDGPU_MAX_IP_NUM)
-               return -EINVAL;
-
-       if (ring >= AMDGPU_MAX_RINGS)
-               return -EINVAL;
-
-       /* Right now all IPs have only one instance - multiple rings. */
-       if (instance != 0) {
-               DRM_DEBUG("invalid ip instance: %d\n", instance);
-               return -EINVAL;
-       }
-
-       switch (hw_ip) {
-       case AMDGPU_HW_IP_GFX:
-               ip_num_rings = adev->gfx.num_gfx_rings;
-               break;
-       case AMDGPU_HW_IP_COMPUTE:
-               ip_num_rings = adev->gfx.num_compute_rings;
-               break;
-       case AMDGPU_HW_IP_DMA:
-               ip_num_rings = adev->sdma.num_instances;
-               break;
-       case AMDGPU_HW_IP_UVD:
-               for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
-                       if (!(adev->uvd.harvest_config & (1 << i)))
-                               ip_num_rings++;
-               }
-               break;
-       case AMDGPU_HW_IP_VCE:
-               ip_num_rings = adev->vce.num_rings;
-               break;
-       case AMDGPU_HW_IP_UVD_ENC:
-               for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
-                       if (!(adev->uvd.harvest_config & (1 << i)))
-                               ip_num_rings++;
-               }
-               ip_num_rings =
-                       adev->uvd.num_enc_rings * ip_num_rings;
-               break;
-       case AMDGPU_HW_IP_VCN_DEC:
-               ip_num_rings = 1;
-               break;
-       case AMDGPU_HW_IP_VCN_ENC:
-               ip_num_rings = adev->vcn.num_enc_rings;
-               break;
-       case AMDGPU_HW_IP_VCN_JPEG:
-               ip_num_rings = 1;
-               break;
-       default:
-               DRM_DEBUG("unknown ip type: %d\n", hw_ip);
-               return -EINVAL;
-       }
-
-       if (ring >= ip_num_rings) {
-               DRM_DEBUG("Ring index:%d exceeds maximum:%d for ip:%d\n",
-                         ring, ip_num_rings, hw_ip);
-               return -EINVAL;
-       }
-
-       mutex_lock(&mapper->lock);
-
-       *out_ring = amdgpu_get_cached_map(mapper, ring);
-       if (*out_ring) {
-               /* cache hit */
-               r = 0;
-               goto out_unlock;
-       }
-
-       switch (mapper->hw_ip) {
-       case AMDGPU_HW_IP_GFX:
-       case AMDGPU_HW_IP_UVD:
-       case AMDGPU_HW_IP_VCE:
-       case AMDGPU_HW_IP_UVD_ENC:
-       case AMDGPU_HW_IP_VCN_DEC:
-       case AMDGPU_HW_IP_VCN_ENC:
-       case AMDGPU_HW_IP_VCN_JPEG:
-               r = amdgpu_identity_map(adev, mapper, ring, out_ring);
-               break;
-       case AMDGPU_HW_IP_DMA:
-               r = amdgpu_lru_map(adev, mapper, ring, false, out_ring);
-               break;
-       case AMDGPU_HW_IP_COMPUTE:
-               r = amdgpu_lru_map(adev, mapper, ring, true, out_ring);
-               break;
-       default:
-               *out_ring = NULL;
-               r = -EINVAL;
-               DRM_DEBUG("unknown HW IP type: %d\n", mapper->hw_ip);
-       }
-
-out_unlock:
-       mutex_unlock(&mapper->lock);
-       return r;
-}