drm/i915: No LLC_MLC for HSW.

The mid-level cache or as it's more commonly referred to now as L3, is
not setup this way on HSW.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index df470b5e8d36a0dac1daeaa71576cbfa066a2958..c040aad0cca6652f64ae1198e2ce8868a9e300ea 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -217,7 +217,11 @@ void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
 
        switch (cache_level) {
        case I915_CACHE_LLC_MLC:
-               pte_flags |= GEN6_PTE_CACHE_LLC_MLC;
+               /* Haswell doesn't set L3 this way */
+               if (IS_HASWELL(obj->base.dev))
+                       pte_flags |= GEN6_PTE_CACHE_LLC;
+               else
+                       pte_flags |= GEN6_PTE_CACHE_LLC_MLC;
                break;
        case I915_CACHE_LLC:
                pte_flags |= GEN6_PTE_CACHE_LLC;
@@ -252,12 +256,12 @@ static unsigned int cache_level_to_agp_type(struct drm_device *dev,
 {
        switch (cache_level) {
        case I915_CACHE_LLC_MLC:
-               if (INTEL_INFO(dev)->gen >= 6)
-                       return AGP_USER_CACHED_MEMORY_LLC_MLC;
                /* Older chipsets do not have this extra level of CPU
                 * cacheing, so fallthrough and request the PTE simply
                 * as cached.
                 */
+               if (INTEL_INFO(dev)->gen >= 6 && !IS_HASWELL(dev))
+                       return AGP_USER_CACHED_MEMORY_LLC_MLC;
        case I915_CACHE_LLC:
                return AGP_USER_CACHED_MEMORY;
        default: