[ARM SMP] Add Realview MPcore SMP support
authorRussell King <rmk@dyn-67.arm.linux.org.uk>
Mon, 7 Nov 2005 21:05:42 +0000 (21:05 +0000)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Mon, 7 Nov 2005 21:05:42 +0000 (21:05 +0000)
Add SMP support for the MPcore tile fitted to the Realview ARM
platform.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
arch/arm/mach-realview/Makefile
arch/arm/mach-realview/headsmp.S [new file with mode: 0644]
arch/arm/mach-realview/platsmp.c [new file with mode: 0644]
arch/arm/mm/proc-v6.S
include/asm-arm/arch-realview/entry-macro.S
include/asm-arm/arch-realview/platform.h
include/asm-arm/arch-realview/smp.h [new file with mode: 0644]
include/asm-arm/hardware/arm_scu.h [new file with mode: 0644]

index 8d37ea1605fdc8d08b67c01551c12d32a91bdd66..011a85c1062746f050cabf4cf581beb7424df3be 100644 (file)
@@ -4,3 +4,4 @@
 
 obj-y                                  := core.o clock.o
 obj-$(CONFIG_MACH_REALVIEW_EB)         += realview_eb.o
+obj-$(CONFIG_SMP)                      += platsmp.o headsmp.o
diff --git a/arch/arm/mach-realview/headsmp.S b/arch/arm/mach-realview/headsmp.S
new file mode 100644 (file)
index 0000000..4075473
--- /dev/null
@@ -0,0 +1,39 @@
+/*
+ *  linux/arch/arm/mach-realview/headsmp.S
+ *
+ *  Copyright (c) 2003 ARM Limited
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+       __INIT
+
+/*
+ * Realview specific entry point for secondary CPUs.  This provides
+ * a "holding pen" into which all secondary cores are held until we're
+ * ready for them to initialise.
+ */
+ENTRY(realview_secondary_startup)
+       mrc     p15, 0, r0, c0, c0, 5
+       and     r0, r0, #15
+       adr     r4, 1f
+       ldmia   r4, {r5, r6}
+       sub     r4, r4, r5
+       add     r6, r6, r4
+pen:   ldr     r7, [r6]
+       cmp     r7, r0
+       bne     pen
+
+       /*
+        * we've been released from the holding pen: secondary_stack
+        * should now contain the SVC stack for this core
+        */
+       b       secondary_startup
+
+1:     .long   .
+       .long   pen_release
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c
new file mode 100644 (file)
index 0000000..9844644
--- /dev/null
@@ -0,0 +1,195 @@
+/*
+ *  linux/arch/arm/mach-realview/platsmp.c
+ *
+ *  Copyright (C) 2002 ARM Ltd.
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/smp.h>
+
+#include <asm/cacheflush.h>
+#include <asm/hardware/arm_scu.h>
+#include <asm/hardware.h>
+
+#include "core.h"
+
+extern void realview_secondary_startup(void);
+
+/*
+ * control for which core is the next to come out of the secondary
+ * boot "holding pen"
+ */
+volatile int __cpuinitdata pen_release = -1;
+
+static unsigned int __init get_core_count(void)
+{
+       unsigned int ncores;
+
+       ncores = __raw_readl(IO_ADDRESS(REALVIEW_MPCORE_SCU_BASE) + SCU_CONFIG);
+
+       return (ncores & 0x03) + 1;
+}
+
+static DEFINE_SPINLOCK(boot_lock);
+
+void __cpuinit platform_secondary_init(unsigned int cpu)
+{
+       /*
+        * the primary core may have used a "cross call" soft interrupt
+        * to get this processor out of WFI in the BootMonitor - make
+        * sure that we are no longer being sent this soft interrupt
+        */
+       smp_cross_call_done(cpumask_of_cpu(cpu));
+
+       /*
+        * if any interrupts are already enabled for the primary
+        * core (e.g. timer irq), then they will not have been enabled
+        * for us: do so
+        */
+       gic_cpu_init(__io_address(REALVIEW_GIC_CPU_BASE));
+
+       /*
+        * let the primary processor know we're out of the
+        * pen, then head off into the C entry point
+        */
+       pen_release = -1;
+
+       /*
+        * Synchronise with the boot thread.
+        */
+       spin_lock(&boot_lock);
+       spin_unlock(&boot_lock);
+}
+
+int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+       unsigned long timeout;
+
+       /*
+        * set synchronisation state between this boot processor
+        * and the secondary one
+        */
+       spin_lock(&boot_lock);
+
+       /*
+        * The secondary processor is waiting to be released from
+        * the holding pen - release it, then wait for it to flag
+        * that it has been released by resetting pen_release.
+        *
+        * Note that "pen_release" is the hardware CPU ID, whereas
+        * "cpu" is Linux's internal ID.
+        */
+       pen_release = cpu;
+       flush_cache_all();
+
+       /*
+        * XXX
+        *
+        * This is a later addition to the booting protocol: the
+        * bootMonitor now puts secondary cores into WFI, so
+        * poke_milo() no longer gets the cores moving; we need
+        * to send a soft interrupt to wake the secondary core.
+        * Use smp_cross_call() for this, since there's little
+        * point duplicating the code here
+        */
+       smp_cross_call(cpumask_of_cpu(cpu));
+
+       timeout = jiffies + (1 * HZ);
+       while (time_before(jiffies, timeout)) {
+               if (pen_release == -1)
+                       break;
+
+               udelay(10);
+       }
+
+       /*
+        * now the secondary core is starting up let it run its
+        * calibrations, then wait for it to finish
+        */
+       spin_unlock(&boot_lock);
+
+       return pen_release != -1 ? -ENOSYS : 0;
+}
+
+static void __init poke_milo(void)
+{
+       extern void secondary_startup(void);
+
+       /* nobody is to be released from the pen yet */
+       pen_release = -1;
+
+       /*
+        * write the address of secondary startup into the system-wide
+        * flags register, then clear the bottom two bits, which is what
+        * BootMonitor is waiting for
+        */
+#if 1
+#define REALVIEW_SYS_FLAGSS_OFFSET 0x30
+       __raw_writel(virt_to_phys(realview_secondary_startup),
+                    (IO_ADDRESS(REALVIEW_SYS_BASE) +
+                     REALVIEW_SYS_FLAGSS_OFFSET));
+#define REALVIEW_SYS_FLAGSC_OFFSET 0x34
+       __raw_writel(3,
+                    (IO_ADDRESS(REALVIEW_SYS_BASE) +
+                     REALVIEW_SYS_FLAGSC_OFFSET));
+#endif
+
+       mb();
+}
+
+void __init smp_prepare_cpus(unsigned int max_cpus)
+{
+       unsigned int ncores = get_core_count();
+       unsigned int cpu = smp_processor_id();
+       int i;
+
+       /* sanity check */
+       if (ncores == 0) {
+               printk(KERN_ERR
+                      "Realview: strange CM count of 0? Default to 1\n");
+
+               ncores = 1;
+       }
+
+       if (ncores > NR_CPUS) {
+               printk(KERN_WARNING
+                      "Realview: no. of cores (%d) greater than configured "
+                      "maximum of %d - clipping\n",
+                      ncores, NR_CPUS);
+               ncores = NR_CPUS;
+       }
+
+       smp_store_cpu_info(cpu);
+
+       /*
+        * are we trying to boot more cores than exist?
+        */
+       if (max_cpus > ncores)
+               max_cpus = ncores;
+
+       /*
+        * Initialise the possible/present maps.
+        * cpu_possible_map describes the set of CPUs which may be present
+        * cpu_present_map describes the set of CPUs populated
+        */
+       for (i = 0; i < max_cpus; i++) {
+               cpu_set(i, cpu_possible_map);
+               cpu_set(i, cpu_present_map);
+       }
+
+       /*
+        * Do we need any more CPUs? If so, then let them know where
+        * to start. Note that, on modern versions of MILO, the "poke"
+        * doesn't actually do anything until each individual core is
+        * sent a soft interrupt to get it out of WFI
+        */
+       if (max_cpus > 1)
+               poke_milo();
+}
index a39d8fa2ede5ece3d56c94414afd71632ea8c41d..92f3ca31b7b90e46c03f05104f6e5d6300d2ce7b 100644 (file)
@@ -12,6 +12,7 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
+#include <asm/hardware/arm_scu.h>
 #include <asm/procinfo.h>
 #include <asm/pgtable.h>
 
@@ -194,6 +195,23 @@ cpu_v6_name:
  *     - cache type register is implemented
  */
 __v6_setup:
+#ifdef CONFIG_SMP
+       /* Set up the SCU on core 0 only */
+       mrc     p15, 0, r0, c0, c0, 5           @ CPU core number
+       ands    r0, r0, #15
+       moveq   r0, #0x10000000 @ SCU_BASE
+       orreq   r0, r0, #0x00100000
+       ldreq   r5, [r0, #SCU_CTRL]
+       orreq   r5, r5, #1
+       streq   r5, [r0, #SCU_CTRL]
+
+#ifndef CONFIG_CPU_DCACHE_DISABLE
+       mrc     p15, 0, r0, c1, c0, 1           @ Enable SMP/nAMP mode
+       orr     r0, r0, #0x20
+       mcr     p15, 0, r0, c1, c0, 1
+#endif
+#endif
+
        mov     r0, #0
        mcr     p15, 0, r0, c7, c14, 0          @ clean+invalidate D cache
        mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
index 2712ba77bb3a6db51f729e0d0aa33f2f43498e51..4df469bf42e2809b84bddce343728b08af3488af 100644 (file)
                cmpcs   \irqnr, \irqnr
 
                .endm
+
+               /* We assume that irqstat (the raw value of the IRQ acknowledge
+                * register) is preserved from the macro above.
+                * If there is an IPI, we immediately signal end of interrupt on the
+                * controller, since this requires the original irqstat value which
+                * we won't easily be able to recreate later.
+                */
+
+               .macro test_for_ipi, irqnr, irqstat, base, tmp
+               bic     \irqnr, \irqstat, #0x1c00
+               cmp     \irqnr, #16
+               strcc   \irqstat, [\base, #GIC_CPU_EOI]
+               cmpcs   \irqnr, \irqnr
+               .endm
index 432260121c8b003922397c3cd45db118d3013fcc..aef9b36b3c3771d891e5d199a1daf817c8033b1a 100644 (file)
 #define REALVIEW_GIC_CPU_BASE         0x10040000       /* Generic interrupt controller CPU interface */
 #define REALVIEW_GIC_DIST_BASE        0x10041000       /* Generic interrupt controller distributor */
 #else
+#define REALVIEW_MPCORE_SCU_BASE       0x10100000      /*  SCU registers */
 #define REALVIEW_GIC_CPU_BASE          0x10100100      /* Generic interrupt controller CPU interface */
 #define REALVIEW_GIC_DIST_BASE         0x10101000      /* Generic interrupt controller distributor */
 #endif
diff --git a/include/asm-arm/arch-realview/smp.h b/include/asm-arm/arch-realview/smp.h
new file mode 100644 (file)
index 0000000..fc87783
--- /dev/null
@@ -0,0 +1,31 @@
+#ifndef ASMARM_ARCH_SMP_H
+#define ASMARM_ARCH_SMP_H
+
+#include <linux/config.h>
+
+#include <asm/hardware/gic.h>
+
+#define hard_smp_processor_id()                        \
+       ({                                              \
+               unsigned int cpunum;                    \
+               __asm__("mrc p15, 0, %0, c0, c0, 5"     \
+                       : "=r" (cpunum));               \
+               cpunum &= 0x0F;                         \
+       })
+
+/*
+ * We use IRQ1 as the IPI
+ */
+static inline void smp_cross_call(cpumask_t callmap)
+{
+       gic_raise_softirq(callmap, 1);
+}
+
+/*
+ * Do nothing on MPcore.
+ */
+static inline void smp_cross_call_done(cpumask_t callmap)
+{
+}
+
+#endif
diff --git a/include/asm-arm/hardware/arm_scu.h b/include/asm-arm/hardware/arm_scu.h
new file mode 100644 (file)
index 0000000..9903f60
--- /dev/null
@@ -0,0 +1,13 @@
+#ifndef ASMARM_HARDWARE_ARM_SCU_H
+#define ASMARM_HARDWARE_ARM_SCU_H
+
+/*
+ * SCU registers
+ */
+#define SCU_CTRL               0x00
+#define SCU_CONFIG             0x04
+#define SCU_CPU_STATUS         0x08
+#define SCU_INVALIDATE         0x0c
+#define SCU_FPGA_REVISION      0x10
+
+#endif