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drm/msm/adreno: Move hwcg regs to a6xx hw catalog
authorRob Clark <robdclark@chromium.org>
Tue, 18 Jun 2024 16:42:49 +0000 (09:42 -0700)
committerRob Clark <robdclark@chromium.org>
Thu, 20 Jun 2024 16:45:25 +0000 (09:45 -0700)
Move the hwcg tables into the hw catalog.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/599727/

drivers/gpu/drm/msm/adreno/a6xx_catalog.c patch | blob | blame | history
drivers/gpu/drm/msm/adreno/a6xx_gpu.c patch | blob | blame | history
drivers/gpu/drm/msm/adreno/adreno_gpu.h patch | blob | blame | history

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
index 10a92eab0232d21f9f044dcbd04dc64f0265ad4c..bcc2f4d8cfc6b27ed28436e69074d2a732df65e8 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
@@ -7,6 +7,451 @@
  */
 
 #include "adreno_gpu.h"
+#include "a6xx.xml.h"
+#include "a6xx_gmu.xml.h"
+
+static const struct adreno_reglist a612_hwcg[] = {
+       {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
+       {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000081},
+       {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf},
+       {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
+       {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
+       {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
+       {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
+       {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
+       {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
+       {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
+       {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
+       {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
+       {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01202222},
+       {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
+       {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00},
+       {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022},
+       {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
+       {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
+       {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
+       {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
+       {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
+       {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222},
+       {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
+       {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
+       {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
+       {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
+       {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
+       {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
+       {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
+       {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
+       {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
+       {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
+       {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
+       {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
+       {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
+       {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
+       {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
+       {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
+       {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
+       {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
+       {},
+};
+
+/* For a615 family (a615, a616, a618 and a619) */
+static const struct adreno_reglist a615_hwcg[] = {
+       {REG_A6XX_RBBM_CLOCK_CNTL_SP0,  0x02222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
+       {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
+       {REG_A6XX_RBBM_CLOCK_HYST_SP0,  0x0000F3CF},
+       {REG_A6XX_RBBM_CLOCK_CNTL_TP0,  0x02222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL_TP1,  0x02222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
+       {REG_A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222},
+       {REG_A6XX_RBBM_CLOCK_HYST_TP0,  0x77777777},
+       {REG_A6XX_RBBM_CLOCK_HYST_TP1,  0x77777777},
+       {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
+       {REG_A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},
+       {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
+       {REG_A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777},
+       {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
+       {REG_A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777},
+       {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
+       {REG_A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},
+       {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
+       {REG_A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},
+       {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
+       {REG_A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111},
+       {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
+       {REG_A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111},
+       {REG_A6XX_RBBM_CLOCK_CNTL_UCHE,  0x22222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
+       {REG_A6XX_RBBM_CLOCK_HYST_UCHE,  0x00000004},
+       {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
+       {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222},
+       {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002020},
+       {REG_A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220},
+       {REG_A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220},
+       {REG_A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220},
+       {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
+       {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040F00},
+       {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040F00},
+       {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040F00},
+       {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022},
+       {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
+       {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
+       {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
+       {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
+       {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
+       {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
+       {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
+       {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
+       {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
+       {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
+       {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
+       {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
+       {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
+       {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
+       {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
+       {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
+       {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
+       {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
+       {},
+};
+
+static const struct adreno_reglist a630_hwcg[] = {
+       {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL_SP1, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL_SP2, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL_SP3, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022220},
+       {REG_A6XX_RBBM_CLOCK_CNTL2_SP1, 0x02022220},
+       {REG_A6XX_RBBM_CLOCK_CNTL2_SP2, 0x02022220},
+       {REG_A6XX_RBBM_CLOCK_CNTL2_SP3, 0x02022220},
+       {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
+       {REG_A6XX_RBBM_CLOCK_DELAY_SP1, 0x00000080},
+       {REG_A6XX_RBBM_CLOCK_DELAY_SP2, 0x00000080},
+       {REG_A6XX_RBBM_CLOCK_DELAY_SP3, 0x00000080},
+       {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf},
+       {REG_A6XX_RBBM_CLOCK_HYST_SP1, 0x0000f3cf},
+       {REG_A6XX_RBBM_CLOCK_HYST_SP2, 0x0000f3cf},
+       {REG_A6XX_RBBM_CLOCK_HYST_SP3, 0x0000f3cf},
+       {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL_TP2, 0x02222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL_TP3, 0x02222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL2_TP2, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL2_TP3, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL3_TP2, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL3_TP3, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
+       {REG_A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222},
+       {REG_A6XX_RBBM_CLOCK_CNTL4_TP2, 0x00022222},
+       {REG_A6XX_RBBM_CLOCK_CNTL4_TP3, 0x00022222},
+       {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
+       {REG_A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777},
+       {REG_A6XX_RBBM_CLOCK_HYST_TP2, 0x77777777},
+       {REG_A6XX_RBBM_CLOCK_HYST_TP3, 0x77777777},
+       {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
+       {REG_A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},
+       {REG_A6XX_RBBM_CLOCK_HYST2_TP2, 0x77777777},
+       {REG_A6XX_RBBM_CLOCK_HYST2_TP3, 0x77777777},
+       {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
+       {REG_A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777},
+       {REG_A6XX_RBBM_CLOCK_HYST3_TP2, 0x77777777},
+       {REG_A6XX_RBBM_CLOCK_HYST3_TP3, 0x77777777},
+       {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
+       {REG_A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777},
+       {REG_A6XX_RBBM_CLOCK_HYST4_TP2, 0x00077777},
+       {REG_A6XX_RBBM_CLOCK_HYST4_TP3, 0x00077777},
+       {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
+       {REG_A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},
+       {REG_A6XX_RBBM_CLOCK_DELAY_TP2, 0x11111111},
+       {REG_A6XX_RBBM_CLOCK_DELAY_TP3, 0x11111111},
+       {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
+       {REG_A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},
+       {REG_A6XX_RBBM_CLOCK_DELAY2_TP2, 0x11111111},
+       {REG_A6XX_RBBM_CLOCK_DELAY2_TP3, 0x11111111},
+       {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
+       {REG_A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111},
+       {REG_A6XX_RBBM_CLOCK_DELAY3_TP2, 0x11111111},
+       {REG_A6XX_RBBM_CLOCK_DELAY3_TP3, 0x11111111},
+       {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
+       {REG_A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111},
+       {REG_A6XX_RBBM_CLOCK_DELAY4_TP2, 0x00011111},
+       {REG_A6XX_RBBM_CLOCK_DELAY4_TP3, 0x00011111},
+       {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
+       {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
+       {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
+       {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL_RB1, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL_RB2, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL_RB3, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222},
+       {REG_A6XX_RBBM_CLOCK_CNTL2_RB1, 0x00002222},
+       {REG_A6XX_RBBM_CLOCK_CNTL2_RB2, 0x00002222},
+       {REG_A6XX_RBBM_CLOCK_CNTL2_RB3, 0x00002222},
+       {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
+       {REG_A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220},
+       {REG_A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220},
+       {REG_A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220},
+       {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00},
+       {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040f00},
+       {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040f00},
+       {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040f00},
+       {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022},
+       {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
+       {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
+       {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
+       {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
+       {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
+       {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
+       {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
+       {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
+       {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
+       {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
+       {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
+       {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
+       {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
+       {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
+       {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
+       {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
+       {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
+       {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
+       {},
+};
+
+static const struct adreno_reglist a640_hwcg[] = {
+       {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
+       {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
+       {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
+       {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
+       {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
+       {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
+       {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
+       {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
+       {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
+       {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
+       {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
+       {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
+       {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
+       {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
+       {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
+       {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05222022},
+       {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
+       {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
+       {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
+       {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
+       {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
+       {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
+       {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
+       {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
+       {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
+       {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
+       {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
+       {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
+       {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
+       {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
+       {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
+       {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
+       {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
+       {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
+       {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
+       {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
+       {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
+       {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
+       {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
+       {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
+       {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
+       {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
+       {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
+       {},
+};
+
+static const struct adreno_reglist a650_hwcg[] = {
+       {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
+       {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
+       {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
+       {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
+       {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
+       {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
+       {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
+       {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
+       {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
+       {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
+       {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
+       {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
+       {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
+       {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
+       {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
+       {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
+       {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
+       {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
+       {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
+       {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
+       {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
+       {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
+       {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
+       {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
+       {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
+       {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
+       {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
+       {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
+       {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
+       {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
+       {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
+       {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
+       {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
+       {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
+       {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000777},
+       {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
+       {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
+       {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
+       {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
+       {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
+       {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
+       {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
+       {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
+       {},
+};
+
+static const struct adreno_reglist a660_hwcg[] = {
+       {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
+       {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
+       {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
+       {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
+       {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
+       {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
+       {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
+       {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
+       {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
+       {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
+       {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
+       {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
+       {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
+       {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
+       {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
+       {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
+       {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
+       {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
+       {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
+       {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
+       {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
+       {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
+       {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
+       {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
+       {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
+       {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
+       {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
+       {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
+       {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
+       {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
+       {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
+       {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
+       {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
+       {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
+       {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
+       {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
+       {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
+       {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
+       {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
+       {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
+       {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
+       {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
+       {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
+       {},
+};
+
+static const struct adreno_reglist a690_hwcg[] = {
+       {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
+       {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
+       {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
+       {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
+       {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
+       {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
+       {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
+       {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
+       {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
+       {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
+       {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
+       {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
+       {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
+       {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
+       {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
+       {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
+       {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
+       {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
+       {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
+       {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
+       {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
+       {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
+       {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
+       {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
+       {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
+       {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
+       {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
+       {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
+       {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
+       {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
+       {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
+       {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
+       {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
+       {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
+       {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
+       {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
+       {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
+       {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
+       {REG_A6XX_RBBM_CLOCK_CNTL, 0x8AA8AA82},
+       {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
+       {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
+       {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
+       {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
+       {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
+       {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
+       {REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, 0x20200},
+       {REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, 0x10111},
+       {REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, 0x5555},
+       {}
+};
 
 static const struct adreno_info a6xx_gpus[] = {
        {
@@ -270,6 +715,180 @@ MODULE_FIRMWARE("qcom/a650_sqe.fw");
 MODULE_FIRMWARE("qcom/a660_gmu.bin");
 MODULE_FIRMWARE("qcom/a660_sqe.fw");
 
+static const struct adreno_reglist a702_hwcg[] = {
+       { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222 },
+       { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220 },
+       { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000081 },
+       { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf },
+       { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222 },
+       { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 },
+       { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 },
+       { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222 },
+       { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 },
+       { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 },
+       { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 },
+       { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 },
+       { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 },
+       { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 },
+       { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 },
+       { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 },
+       { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 },
+       { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01202222 },
+       { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 },
+       { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00 },
+       { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022 },
+       { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555 },
+       { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 },
+       { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044 },
+       { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 },
+       { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222 },
+       { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222 },
+       { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002 },
+       { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 },
+       { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000 },
+       { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222 },
+       { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 },
+       { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 },
+       { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 },
+       { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 },
+       { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 },
+       { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 },
+       { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 },
+       { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004 },
+       { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002 },
+       { REG_A6XX_RBBM_ISDB_CNT, 0x00000182 },
+       { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 },
+       { REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 },
+       { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 },
+       { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 },
+       { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 },
+       { REG_A6XX_RBBM_CLOCK_CNTL_FCHE, 0x00000222 },
+       { REG_A6XX_RBBM_CLOCK_DELAY_FCHE, 0x00000000 },
+       { REG_A6XX_RBBM_CLOCK_HYST_FCHE, 0x00000000 },
+       { REG_A6XX_RBBM_CLOCK_CNTL_GLC, 0x00222222 },
+       { REG_A6XX_RBBM_CLOCK_DELAY_GLC, 0x00000000 },
+       { REG_A6XX_RBBM_CLOCK_HYST_GLC, 0x00000000 },
+       { REG_A6XX_RBBM_CLOCK_CNTL_MHUB, 0x00000002 },
+       { REG_A6XX_RBBM_CLOCK_DELAY_MHUB, 0x00000000 },
+       { REG_A6XX_RBBM_CLOCK_HYST_MHUB, 0x00000000 },
+       {}
+};
+
+static const struct adreno_reglist a730_hwcg[] = {
+       { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222 },
+       { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022222 },
+       { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf },
+       { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080 },
+       { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222220 },
+       { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 },
+       { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 },
+       { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00222222 },
+       { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 },
+       { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 },
+       { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 },
+       { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 },
+       { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 },
+       { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 },
+       { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 },
+       { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 },
+       { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 },
+       { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004 },
+       { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002 },
+       { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 },
+       { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222 },
+       { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 },
+       { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x44000f00 },
+       { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022 },
+       { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00555555 },
+       { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 },
+       { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00440044 },
+       { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 },
+       { REG_A7XX_RBBM_CLOCK_MODE2_GRAS, 0x00000222 },
+       { REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS, 0x00222222 },
+       { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222223 },
+       { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222 },
+       { REG_A7XX_RBBM_CLOCK_MODE_BV_GPC, 0x00222222 },
+       { REG_A7XX_RBBM_CLOCK_MODE_BV_VFD, 0x00002222 },
+       { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 },
+       { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 },
+       { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 },
+       { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000 },
+       { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 },
+       { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222 },
+       { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 },
+       { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 },
+       { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 },
+       { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002 },
+       { REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ, 0x55555552 },
+       { REG_A7XX_RBBM_CLOCK_MODE_CP, 0x00000223 },
+       { REG_A6XX_RBBM_CLOCK_CNTL, 0x8aa8aa82 },
+       { REG_A6XX_RBBM_ISDB_CNT, 0x00000182 },
+       { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 },
+       { REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 },
+       { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 },
+       { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 },
+       { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 },
+       {},
+};
+
+static const struct adreno_reglist a740_hwcg[] = {
+       { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222 },
+       { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x22022222 },
+       { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x003cf3cf },
+       { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080 },
+       { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222220 },
+       { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 },
+       { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 },
+       { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00222222 },
+       { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 },
+       { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 },
+       { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 },
+       { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 },
+       { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 },
+       { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 },
+       { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 },
+       { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 },
+       { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 },
+       { REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x00222222 },
+       { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000444 },
+       { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000222 },
+       { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 },
+       { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222 },
+       { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 },
+       { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x44000f00 },
+       { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022 },
+       { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00555555 },
+       { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 },
+       { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00440044 },
+       { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 },
+       { REG_A7XX_RBBM_CLOCK_MODE2_GRAS, 0x00000222 },
+       { REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS, 0x00222222 },
+       { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222223 },
+       { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00222222 },
+       { REG_A7XX_RBBM_CLOCK_MODE_BV_GPC, 0x00222222 },
+       { REG_A7XX_RBBM_CLOCK_MODE_BV_VFD, 0x00002222 },
+       { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 },
+       { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 },
+       { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 },
+       { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00000000 },
+       { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 },
+       { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00000000 },
+       { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 },
+       { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 },
+       { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 },
+       { REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ, 0x55555552 },
+       { REG_A7XX_RBBM_CLOCK_HYST2_VFD, 0x00000000 },
+       { REG_A7XX_RBBM_CLOCK_MODE_CP, 0x00000222 },
+       { REG_A6XX_RBBM_CLOCK_CNTL, 0x8aa8aa82 },
+       { REG_A6XX_RBBM_ISDB_CNT, 0x00000182 },
+       { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 },
+       { REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 },
+       { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 },
+       { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 },
+       { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 },
+       {},
+};
+
 static const struct adreno_info a7xx_gpus[] = {
        {
                .chip_ids = ADRENO_CHIP_IDS(0x07000200),
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 973872ad0474e9df4375760dd8ae5e653397f45b..99310786ecd71d31736d6821fcdf45ab725c41b0 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -394,623 +394,6 @@ static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
        a6xx_flush(gpu, ring);
 }
 
-const struct adreno_reglist a612_hwcg[] = {
-       {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
-       {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000081},
-       {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf},
-       {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
-       {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
-       {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
-       {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
-       {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
-       {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
-       {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
-       {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
-       {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
-       {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01202222},
-       {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
-       {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00},
-       {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022},
-       {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
-       {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
-       {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
-       {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
-       {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
-       {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222},
-       {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
-       {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
-       {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
-       {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
-       {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
-       {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
-       {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
-       {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
-       {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
-       {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
-       {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
-       {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
-       {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
-       {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
-       {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
-       {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
-       {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
-       {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
-       {},
-};
-
-/* For a615 family (a615, a616, a618 and a619) */
-const struct adreno_reglist a615_hwcg[] = {
-       {REG_A6XX_RBBM_CLOCK_CNTL_SP0,  0x02222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
-       {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
-       {REG_A6XX_RBBM_CLOCK_HYST_SP0,  0x0000F3CF},
-       {REG_A6XX_RBBM_CLOCK_CNTL_TP0,  0x02222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL_TP1,  0x02222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
-       {REG_A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222},
-       {REG_A6XX_RBBM_CLOCK_HYST_TP0,  0x77777777},
-       {REG_A6XX_RBBM_CLOCK_HYST_TP1,  0x77777777},
-       {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
-       {REG_A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},
-       {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
-       {REG_A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777},
-       {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
-       {REG_A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777},
-       {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
-       {REG_A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},
-       {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
-       {REG_A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},
-       {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
-       {REG_A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111},
-       {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
-       {REG_A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111},
-       {REG_A6XX_RBBM_CLOCK_CNTL_UCHE,  0x22222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
-       {REG_A6XX_RBBM_CLOCK_HYST_UCHE,  0x00000004},
-       {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
-       {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222},
-       {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002020},
-       {REG_A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220},
-       {REG_A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220},
-       {REG_A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220},
-       {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
-       {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040F00},
-       {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040F00},
-       {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040F00},
-       {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022},
-       {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
-       {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
-       {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
-       {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
-       {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
-       {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
-       {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
-       {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
-       {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
-       {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
-       {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
-       {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
-       {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
-       {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
-       {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
-       {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
-       {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
-       {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
-       {},
-};
-
-const struct adreno_reglist a630_hwcg[] = {
-       {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL_SP1, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL_SP2, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL_SP3, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022220},
-       {REG_A6XX_RBBM_CLOCK_CNTL2_SP1, 0x02022220},
-       {REG_A6XX_RBBM_CLOCK_CNTL2_SP2, 0x02022220},
-       {REG_A6XX_RBBM_CLOCK_CNTL2_SP3, 0x02022220},
-       {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
-       {REG_A6XX_RBBM_CLOCK_DELAY_SP1, 0x00000080},
-       {REG_A6XX_RBBM_CLOCK_DELAY_SP2, 0x00000080},
-       {REG_A6XX_RBBM_CLOCK_DELAY_SP3, 0x00000080},
-       {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf},
-       {REG_A6XX_RBBM_CLOCK_HYST_SP1, 0x0000f3cf},
-       {REG_A6XX_RBBM_CLOCK_HYST_SP2, 0x0000f3cf},
-       {REG_A6XX_RBBM_CLOCK_HYST_SP3, 0x0000f3cf},
-       {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL_TP2, 0x02222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL_TP3, 0x02222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL2_TP2, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL2_TP3, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL3_TP2, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL3_TP3, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
-       {REG_A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222},
-       {REG_A6XX_RBBM_CLOCK_CNTL4_TP2, 0x00022222},
-       {REG_A6XX_RBBM_CLOCK_CNTL4_TP3, 0x00022222},
-       {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
-       {REG_A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777},
-       {REG_A6XX_RBBM_CLOCK_HYST_TP2, 0x77777777},
-       {REG_A6XX_RBBM_CLOCK_HYST_TP3, 0x77777777},
-       {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
-       {REG_A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},
-       {REG_A6XX_RBBM_CLOCK_HYST2_TP2, 0x77777777},
-       {REG_A6XX_RBBM_CLOCK_HYST2_TP3, 0x77777777},
-       {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
-       {REG_A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777},
-       {REG_A6XX_RBBM_CLOCK_HYST3_TP2, 0x77777777},
-       {REG_A6XX_RBBM_CLOCK_HYST3_TP3, 0x77777777},
-       {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
-       {REG_A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777},
-       {REG_A6XX_RBBM_CLOCK_HYST4_TP2, 0x00077777},
-       {REG_A6XX_RBBM_CLOCK_HYST4_TP3, 0x00077777},
-       {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
-       {REG_A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},
-       {REG_A6XX_RBBM_CLOCK_DELAY_TP2, 0x11111111},
-       {REG_A6XX_RBBM_CLOCK_DELAY_TP3, 0x11111111},
-       {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
-       {REG_A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},
-       {REG_A6XX_RBBM_CLOCK_DELAY2_TP2, 0x11111111},
-       {REG_A6XX_RBBM_CLOCK_DELAY2_TP3, 0x11111111},
-       {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
-       {REG_A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111},
-       {REG_A6XX_RBBM_CLOCK_DELAY3_TP2, 0x11111111},
-       {REG_A6XX_RBBM_CLOCK_DELAY3_TP3, 0x11111111},
-       {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
-       {REG_A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111},
-       {REG_A6XX_RBBM_CLOCK_DELAY4_TP2, 0x00011111},
-       {REG_A6XX_RBBM_CLOCK_DELAY4_TP3, 0x00011111},
-       {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
-       {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
-       {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
-       {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL_RB1, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL_RB2, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL_RB3, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222},
-       {REG_A6XX_RBBM_CLOCK_CNTL2_RB1, 0x00002222},
-       {REG_A6XX_RBBM_CLOCK_CNTL2_RB2, 0x00002222},
-       {REG_A6XX_RBBM_CLOCK_CNTL2_RB3, 0x00002222},
-       {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
-       {REG_A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220},
-       {REG_A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220},
-       {REG_A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220},
-       {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00},
-       {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040f00},
-       {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040f00},
-       {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040f00},
-       {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022},
-       {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
-       {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
-       {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
-       {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
-       {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
-       {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
-       {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
-       {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
-       {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
-       {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
-       {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
-       {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
-       {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
-       {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
-       {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
-       {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
-       {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
-       {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
-       {},
-};
-
-const struct adreno_reglist a640_hwcg[] = {
-       {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
-       {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
-       {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
-       {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
-       {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
-       {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
-       {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
-       {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
-       {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
-       {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
-       {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
-       {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
-       {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
-       {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
-       {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
-       {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05222022},
-       {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
-       {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
-       {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
-       {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
-       {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
-       {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
-       {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
-       {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
-       {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
-       {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
-       {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
-       {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
-       {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
-       {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
-       {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
-       {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
-       {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
-       {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
-       {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
-       {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
-       {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
-       {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
-       {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
-       {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
-       {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
-       {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
-       {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
-       {},
-};
-
-const struct adreno_reglist a650_hwcg[] = {
-       {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
-       {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
-       {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
-       {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
-       {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
-       {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
-       {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
-       {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
-       {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
-       {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
-       {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
-       {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
-       {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
-       {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
-       {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
-       {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
-       {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
-       {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
-       {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
-       {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
-       {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
-       {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
-       {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
-       {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
-       {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
-       {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
-       {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
-       {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
-       {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
-       {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
-       {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
-       {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
-       {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
-       {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
-       {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000777},
-       {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
-       {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
-       {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
-       {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
-       {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
-       {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
-       {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
-       {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
-       {},
-};
-
-const struct adreno_reglist a660_hwcg[] = {
-       {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
-       {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
-       {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
-       {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
-       {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
-       {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
-       {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
-       {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
-       {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
-       {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
-       {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
-       {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
-       {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
-       {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
-       {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
-       {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
-       {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
-       {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
-       {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
-       {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
-       {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
-       {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
-       {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
-       {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
-       {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
-       {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
-       {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
-       {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
-       {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
-       {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
-       {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
-       {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
-       {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
-       {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
-       {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
-       {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
-       {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
-       {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
-       {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
-       {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
-       {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
-       {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
-       {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
-       {},
-};
-
-const struct adreno_reglist a690_hwcg[] = {
-       {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
-       {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
-       {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
-       {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
-       {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
-       {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
-       {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
-       {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
-       {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
-       {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
-       {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
-       {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
-       {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
-       {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
-       {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
-       {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
-       {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
-       {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
-       {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
-       {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
-       {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
-       {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
-       {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
-       {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
-       {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
-       {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
-       {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
-       {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
-       {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
-       {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
-       {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
-       {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
-       {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
-       {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
-       {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
-       {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
-       {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
-       {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
-       {REG_A6XX_RBBM_CLOCK_CNTL, 0x8AA8AA82},
-       {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
-       {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
-       {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
-       {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
-       {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
-       {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
-       {REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, 0x20200},
-       {REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, 0x10111},
-       {REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, 0x5555},
-       {}
-};
-
-const struct adreno_reglist a702_hwcg[] = {
-       { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222 },
-       { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220 },
-       { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000081 },
-       { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf },
-       { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222 },
-       { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 },
-       { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 },
-       { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222 },
-       { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 },
-       { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 },
-       { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 },
-       { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 },
-       { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 },
-       { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 },
-       { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 },
-       { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 },
-       { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 },
-       { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01202222 },
-       { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 },
-       { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00 },
-       { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022 },
-       { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555 },
-       { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 },
-       { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044 },
-       { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 },
-       { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222 },
-       { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222 },
-       { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002 },
-       { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 },
-       { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000 },
-       { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222 },
-       { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 },
-       { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 },
-       { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 },
-       { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 },
-       { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 },
-       { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 },
-       { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 },
-       { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004 },
-       { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002 },
-       { REG_A6XX_RBBM_ISDB_CNT, 0x00000182 },
-       { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 },
-       { REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 },
-       { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 },
-       { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 },
-       { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 },
-       { REG_A6XX_RBBM_CLOCK_CNTL_FCHE, 0x00000222 },
-       { REG_A6XX_RBBM_CLOCK_DELAY_FCHE, 0x00000000 },
-       { REG_A6XX_RBBM_CLOCK_HYST_FCHE, 0x00000000 },
-       { REG_A6XX_RBBM_CLOCK_CNTL_GLC, 0x00222222 },
-       { REG_A6XX_RBBM_CLOCK_DELAY_GLC, 0x00000000 },
-       { REG_A6XX_RBBM_CLOCK_HYST_GLC, 0x00000000 },
-       { REG_A6XX_RBBM_CLOCK_CNTL_MHUB, 0x00000002 },
-       { REG_A6XX_RBBM_CLOCK_DELAY_MHUB, 0x00000000 },
-       { REG_A6XX_RBBM_CLOCK_HYST_MHUB, 0x00000000 },
-       {}
-};
-
-const struct adreno_reglist a730_hwcg[] = {
-       { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222 },
-       { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022222 },
-       { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf },
-       { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080 },
-       { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222220 },
-       { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 },
-       { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 },
-       { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00222222 },
-       { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 },
-       { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 },
-       { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 },
-       { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 },
-       { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 },
-       { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 },
-       { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 },
-       { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 },
-       { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 },
-       { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004 },
-       { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002 },
-       { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 },
-       { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222 },
-       { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 },
-       { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x44000f00 },
-       { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022 },
-       { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00555555 },
-       { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 },
-       { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00440044 },
-       { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 },
-       { REG_A7XX_RBBM_CLOCK_MODE2_GRAS, 0x00000222 },
-       { REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS, 0x00222222 },
-       { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222223 },
-       { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222 },
-       { REG_A7XX_RBBM_CLOCK_MODE_BV_GPC, 0x00222222 },
-       { REG_A7XX_RBBM_CLOCK_MODE_BV_VFD, 0x00002222 },
-       { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 },
-       { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 },
-       { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 },
-       { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000 },
-       { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 },
-       { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222 },
-       { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 },
-       { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 },
-       { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 },
-       { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002 },
-       { REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ, 0x55555552 },
-       { REG_A7XX_RBBM_CLOCK_MODE_CP, 0x00000223 },
-       { REG_A6XX_RBBM_CLOCK_CNTL, 0x8aa8aa82 },
-       { REG_A6XX_RBBM_ISDB_CNT, 0x00000182 },
-       { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 },
-       { REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 },
-       { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 },
-       { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 },
-       { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 },
-       {},
-};
-
-const struct adreno_reglist a740_hwcg[] = {
-       { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222 },
-       { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x22022222 },
-       { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x003cf3cf },
-       { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080 },
-       { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222220 },
-       { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 },
-       { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 },
-       { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00222222 },
-       { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 },
-       { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 },
-       { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 },
-       { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 },
-       { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 },
-       { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 },
-       { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 },
-       { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 },
-       { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 },
-       { REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x00222222 },
-       { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000444 },
-       { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000222 },
-       { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 },
-       { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222 },
-       { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 },
-       { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x44000f00 },
-       { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022 },
-       { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00555555 },
-       { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 },
-       { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00440044 },
-       { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 },
-       { REG_A7XX_RBBM_CLOCK_MODE2_GRAS, 0x00000222 },
-       { REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS, 0x00222222 },
-       { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222223 },
-       { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00222222 },
-       { REG_A7XX_RBBM_CLOCK_MODE_BV_GPC, 0x00222222 },
-       { REG_A7XX_RBBM_CLOCK_MODE_BV_VFD, 0x00002222 },
-       { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 },
-       { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 },
-       { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 },
-       { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00000000 },
-       { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 },
-       { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00000000 },
-       { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 },
-       { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 },
-       { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 },
-       { REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ, 0x55555552 },
-       { REG_A7XX_RBBM_CLOCK_HYST2_VFD, 0x00000000 },
-       { REG_A7XX_RBBM_CLOCK_MODE_CP, 0x00000222 },
-       { REG_A6XX_RBBM_CLOCK_CNTL, 0x8aa8aa82 },
-       { REG_A6XX_RBBM_ISDB_CNT, 0x00000182 },
-       { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 },
-       { REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 },
-       { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 },
-       { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 },
-       { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 },
-       {},
-};
-
 static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
 {
        struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index 17aba8c58f3d4ac662d05159746fa95c31b11504..695e00ae1f62f8de6a4c187e8e3c3435c7e4d8c3 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -77,9 +77,6 @@ struct adreno_reglist {
        u32 value;
 };
 
-extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[];
-extern const struct adreno_reglist a660_hwcg[], a690_hwcg[], a702_hwcg[], a730_hwcg[], a740_hwcg[];
-
 struct adreno_speedbin {
        uint16_t fuse;
        uint16_t speedbin;
Linux 6.x block layer and io_uring tree(s)