drm/amd/display: Add monitor patch for AUO dpcd issue

[Why]
dpcd cap mismatch in 2200 vs base

[How]
Add monitor patch which using based caps to overwrite 2200

Signed-off-by: Lewis Huang <Lewis.Huang@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 26dce397c34cbfb55edab28cff0dba1e3251ea63..e5807be78edb0f1278772f08f179c7424a11f782 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3371,3 +3371,10 @@ const struct dc_link_settings *dc_link_get_link_cap(
                return &link->preferred_link_setting;
        return &link->verified_link_cap;
 }
+
+void dc_link_overwrite_extended_receiver_cap(
+               struct dc_link *link)
+{
+       dp_overwrite_extended_receiver_cap(link);
+}
+

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 8c257a9f4c7fd553f0e90cdc069109308f52d6f0..2124bc10fc53050145c25fa035890c8362bd11be 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -3446,6 +3446,68 @@ static bool retrieve_link_cap(struct dc_link *link)
        return true;
 }
 
+bool dp_overwrite_extended_receiver_cap(struct dc_link *link)
+{
+       uint8_t dpcd_data[16];
+       uint32_t read_dpcd_retry_cnt = 3;
+       enum dc_status status = DC_ERROR_UNEXPECTED;
+       union dp_downstream_port_present ds_port = { 0 };
+       union down_stream_port_count down_strm_port_count;
+       union edp_configuration_cap edp_config_cap;
+
+       int i;
+
+       for (i = 0; i < read_dpcd_retry_cnt; i++) {
+               status = core_link_read_dpcd(
+                               link,
+                               DP_DPCD_REV,
+                               dpcd_data,
+                               sizeof(dpcd_data));
+               if (status == DC_OK)
+                       break;
+       }
+
+       link->dpcd_caps.dpcd_rev.raw =
+               dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
+
+       if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
+               return false;
+
+       ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
+                       DP_DPCD_REV];
+
+       get_active_converter_info(ds_port.byte, link);
+
+       down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
+                       DP_DPCD_REV];
+
+       link->dpcd_caps.allow_invalid_MSA_timing_param =
+               down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
+
+       link->dpcd_caps.max_ln_count.raw = dpcd_data[
+               DP_MAX_LANE_COUNT - DP_DPCD_REV];
+
+       link->dpcd_caps.max_down_spread.raw = dpcd_data[
+               DP_MAX_DOWNSPREAD - DP_DPCD_REV];
+
+       link->reported_link_cap.lane_count =
+               link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
+       link->reported_link_cap.link_rate = dpcd_data[
+               DP_MAX_LINK_RATE - DP_DPCD_REV];
+       link->reported_link_cap.link_spread =
+               link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
+               LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
+
+       edp_config_cap.raw = dpcd_data[
+               DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
+       link->dpcd_caps.panel_mode_edp =
+               edp_config_cap.bits.ALT_SCRAMBLER_RESET;
+       link->dpcd_caps.dpcd_display_control_capable =
+               edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
+
+       return true;
+}
+
 bool detect_dp_sink_caps(struct dc_link *link)
 {
        return retrieve_link_cap(link);

diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
index f420aeac7fbd3e13ece81e4a0c0b8859fdd27ded..f9aae35aec921ae0775916e89528f703620939ac 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -301,6 +301,9 @@ uint32_t dc_link_bandwidth_kbps(
 const struct dc_link_settings *dc_link_get_link_cap(
                const struct dc_link *link);
 
+void dc_link_overwrite_extended_receiver_cap(
+               struct dc_link *link);
+
 bool dc_submit_i2c(
                struct dc *dc,
                uint32_t link_index,

diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
index 6198bccd61991e021bc7d4698a6ef79da025547d..8b1f0ce6c2a7fcae890cd364ea5b27f364b7757f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
@@ -76,6 +76,8 @@ void dp_enable_mst_on_sink(struct dc_link *link, bool enable);
 enum dp_panel_mode dp_get_panel_mode(struct dc_link *link);
 void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode);
 
+bool dp_overwrite_extended_receiver_cap(struct dc_link *link);
+
 void dp_set_fec_ready(struct dc_link *link, bool ready);
 void dp_set_fec_enable(struct dc_link *link, bool enable);
 bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable);