drm/amdgpu: fix scratch register access method in SRIOV
authorZhenGuo Yin <zhenguo.yin@amd.com>
Mon, 6 Jun 2022 02:36:13 +0000 (10:36 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 8 Jun 2022 15:41:13 +0000 (11:41 -0400)
The scratch register should be accessed through MMIO instead of RLCG
in SRIOV, since it being used in RLCG register access function.

Fixes: d54762cc3e6a ("drm/amdgpu: nuke dynamic gfx scratch reg allocation")
Signed-off-by: ZhenGuo Yin <zhenguo.yin@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

index 797e90e8ce28bf105a1bbd064f565ebd2765070b..abf2bf7f1a7914d871b183ccee557fc3a21a9b35 100644 (file)
@@ -3780,11 +3780,12 @@ static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
 {
        struct amdgpu_device *adev = ring->adev;
+       uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
        uint32_t tmp = 0;
        unsigned i;
        int r;
 
-       WREG32_SOC15(GC, 0, mmSCRATCH_REG0, 0xCAFEDEAD);
+       WREG32(scratch, 0xCAFEDEAD);
        r = amdgpu_ring_alloc(ring, 3);
        if (r) {
                DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
@@ -3793,13 +3794,13 @@ static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
        }
 
        amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
-       amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0) -
+       amdgpu_ring_write(ring, scratch -
                          PACKET3_SET_UCONFIG_REG_START);
        amdgpu_ring_write(ring, 0xDEADBEEF);
        amdgpu_ring_commit(ring);
 
        for (i = 0; i < adev->usec_timeout; i++) {
-               tmp = RREG32_SOC15(GC, 0, mmSCRATCH_REG0);
+               tmp = RREG32(scratch);
                if (tmp == 0xDEADBEEF)
                        break;
                if (amdgpu_emu_mode == 1)