Merge tag 'soc-fixes-6.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
authorLinus Torvalds <torvalds@linux-foundation.org>
Mon, 19 Dec 2022 22:07:59 +0000 (16:07 -0600)
committerLinus Torvalds <torvalds@linux-foundation.org>
Mon, 19 Dec 2022 22:07:59 +0000 (16:07 -0600)
Pull ARM SoC fixes from Arnd Bergmann:
 "These are a couple of build fixes from randconfig testing, plus a set
  of Mediatek SoC specific fixes, all trivial"

* tag 'soc-fixes-6.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
  soc: tegra: fix CPU_BIG_ENDIAN dependencies
  ARM: disallow pre-ARMv5 builds with ld.lld
  ARM: pxa: fix building with clang
  MAINTAINERS: add related dts to IXP4xx
  ARM: dts: spear: drop 0x from unit address
  arm64: dts: mt8183: Fix Mali GPU clock
  arm64: dts: mediatek: mt8195-demo: fix the memory size of node secmon
  soc: mediatek: pm-domains: Fix the power glitch issue

MAINTAINERS
arch/arm/Kconfig
arch/arm/boot/dts/spear300.dtsi
arch/arm/boot/dts/spear310.dtsi
arch/arm/boot/dts/spear320.dtsi
arch/arm/mach-pxa/pxa27x.c
arch/arm/mach-pxa/pxa3xx.c
arch/arm64/boot/dts/mediatek/mt8183.dtsi
arch/arm64/boot/dts/mediatek/mt8195-demo.dts
drivers/soc/mediatek/mtk-pm-domains.c
drivers/soc/tegra/Kconfig

index 5490b1f9480319ab397fd938421f42b35100dd42..7f0b7181e60a5dcccdb6d2acd3704563742ccea3 100644 (file)
@@ -2330,6 +2330,7 @@ F:        Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.y
 F:     Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt
 F:     Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml
 F:     Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml
+F:     arch/arm/boot/dts/intel-ixp*
 F:     arch/arm/mach-ixp4xx/
 F:     drivers/bus/intel-ixp4xx-eb.c
 F:     drivers/clocksource/timer-ixp4xx.c
index a0da424fc93aac9bc4ad732f3a0dcd04a1155d5a..43c7773b89ae7972d82eb3ab15937bb787d715ed 100644 (file)
@@ -345,12 +345,14 @@ comment "CPU Core family selection"
 config ARCH_MULTI_V4
        bool "ARMv4 based platforms (FA526, StrongARM)"
        depends on !ARCH_MULTI_V6_V7
+       depends on !LD_IS_LLD
        select ARCH_MULTI_V4_V5
        select CPU_FA526 if !(CPU_SA110 || CPU_SA1100)
 
 config ARCH_MULTI_V4T
        bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
        depends on !ARCH_MULTI_V6_V7
+       depends on !LD_IS_LLD
        select ARCH_MULTI_V4_V5
        select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
                CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
index b39bd5a226276f089595704b3b4a71c9bdba3c52..f1135e887f7b8c9f885823b5582cf41879e3abac 100644 (file)
@@ -46,7 +46,7 @@
                        status = "disabled";
                };
 
-               shirq: interrupt-controller@0x50000000 {
+               shirq: interrupt-controller@50000000 {
                        compatible = "st,spear300-shirq";
                        reg = <0x50000000 0x1000>;
                        interrupts = <28>;
index 77570833d46b292fb29204091f861bd0810c275c..ce08d8820940356ae2dbf6ce946a9e275850f68c 100644 (file)
@@ -34,7 +34,7 @@
                        status = "disabled";
                };
 
-               shirq: interrupt-controller@0xb4000000 {
+               shirq: interrupt-controller@b4000000 {
                        compatible = "st,spear310-shirq";
                        reg = <0xb4000000 0x1000>;
                        interrupts = <28 29 30 1>;
index b12474446a48732e44a3fa9af2d350ac002efede..56f141297ea35f4be2013491a49e6e3ac9ddd04c 100644 (file)
@@ -49,7 +49,7 @@
                        status = "disabled";
                };
 
-               shirq: interrupt-controller@0xb3000000 {
+               shirq: interrupt-controller@b3000000 {
                        compatible = "st,spear320-shirq";
                        reg = <0xb3000000 0x1000>;
                        interrupts = <30 28 29 1>;
index afbf6ace954fee1c0bf2faaab889864ee47d01f5..eea507fd5095f47548ea5e69485551d61bed69b2 100644 (file)
@@ -133,8 +133,12 @@ void pxa27x_cpu_pm_enter(suspend_state_t state)
 #ifndef CONFIG_IWMMXT
        u64 acc0;
 
+#ifndef CONFIG_AS_IS_LLVM
        asm volatile(".arch_extension xscale\n\t"
                     "mra %Q0, %R0, acc0" : "=r" (acc0));
+#else
+       asm volatile("mrrc p0, 0, %Q0, %R0, c0" : "=r" (acc0));
+#endif
 #endif
 
        /* ensure voltage-change sequencer not initiated, which hangs */
@@ -153,8 +157,12 @@ void pxa27x_cpu_pm_enter(suspend_state_t state)
        case PM_SUSPEND_MEM:
                cpu_suspend(pwrmode, pxa27x_finish_suspend);
 #ifndef CONFIG_IWMMXT
+#ifndef CONFIG_AS_IS_LLVM
                asm volatile(".arch_extension xscale\n\t"
                             "mar acc0, %Q0, %R0" : "=r" (acc0));
+#else
+               asm volatile("mcrr p0, 0, %Q0, %R0, c0" :: "r" (acc0));
+#endif
 #endif
                break;
        }
index 979642aa7ffe01e29f516ac9c15d3ceb7797af8e..b26f00fc75d54020e62fe038ed58cd35294b8e4c 100644 (file)
@@ -108,8 +108,12 @@ static void pxa3xx_cpu_pm_suspend(void)
 #ifndef CONFIG_IWMMXT
        u64 acc0;
 
+#ifdef CONFIG_CC_IS_GCC
        asm volatile(".arch_extension xscale\n\t"
                     "mra %Q0, %R0, acc0" : "=r" (acc0));
+#else
+       asm volatile("mrrc p0, 0, %Q0, %R0, c0" : "=r" (acc0));
+#endif
 #endif
 
        /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
@@ -137,8 +141,12 @@ static void pxa3xx_cpu_pm_suspend(void)
        AD3ER = 0;
 
 #ifndef CONFIG_IWMMXT
+#ifndef CONFIG_AS_IS_LLVM
        asm volatile(".arch_extension xscale\n\t"
                     "mar acc0, %Q0, %R0" : "=r" (acc0));
+#else
+       asm volatile("mcrr p0, 0, %Q0, %R0, c0" :: "r" (acc0));
+#endif
 #endif
 }
 
index a70b669c49baa3ccc3314320c0c4d2c8841f5c42..402136bfd5350b044d7fb74c6338c3273c14e0f5 100644 (file)
                                <GIC_SPI 278 IRQ_TYPE_LEVEL_LOW>;
                        interrupt-names = "job", "mmu", "gpu";
 
-                       clocks = <&topckgen CLK_TOP_MFGPLL_CK>;
+                       clocks = <&mfgcfg CLK_MFG_BG3D>;
 
                        power-domains =
                                <&spm MT8183_POWER_DOMAIN_MFG_CORE0>,
index 4fbd99eb496a2a19a3c14974af6ec573307ce06d..dec85d2548384ca5ed1ac8e4868d3d20c4f8cc85 100644 (file)
                #size-cells = <2>;
                ranges;
 
-               /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
+               /* 2 MiB reserved for ARM Trusted Firmware (BL31) */
                bl31_secmon_reserved: secmon@54600000 {
                        no-map;
-                       reg = <0 0x54600000 0x0 0x30000>;
+                       reg = <0 0x54600000 0x0 0x200000>;
                };
 
                /* 12 MiB reserved for OP-TEE (BL32)
index 09e3c38b8466434b5dfd9eb732494e028670c59d..474b272f9b02d6cf305f59bf238762d9db93827d 100644 (file)
@@ -275,9 +275,9 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
        clk_bulk_disable_unprepare(pd->num_subsys_clks, pd->subsys_clks);
 
        /* subsys power off */
-       regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT);
        regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT);
        regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_CLK_DIS_BIT);
+       regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT);
        regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_2ND_BIT);
        regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_BIT);
 
index 5f53242946369bc660813ad5ab89768c5f8a7244..3658fb0f0c5b1e50a657b2413684b5fb20ddef88 100644 (file)
@@ -95,6 +95,7 @@ config ARCH_TEGRA_210_SOC
 
 config ARCH_TEGRA_186_SOC
        bool "NVIDIA Tegra186 SoC"
+       depends on !CPU_BIG_ENDIAN
        select MAILBOX
        select TEGRA_BPMP
        select TEGRA_HSP_MBOX
@@ -110,6 +111,7 @@ config ARCH_TEGRA_186_SOC
 
 config ARCH_TEGRA_194_SOC
        bool "NVIDIA Tegra194 SoC"
+       depends on !CPU_BIG_ENDIAN
        select MAILBOX
        select PINCTRL_TEGRA194
        select TEGRA_BPMP
@@ -121,6 +123,7 @@ config ARCH_TEGRA_194_SOC
 
 config ARCH_TEGRA_234_SOC
        bool "NVIDIA Tegra234 SoC"
+       depends on !CPU_BIG_ENDIAN
        select MAILBOX
        select TEGRA_BPMP
        select TEGRA_HSP_MBOX