arm64: dts: imx8mm-kontron: Add support for reading SD_VSEL signal

This fixes the LDO5 regulator handling of the pca9450 driver by
taking the status of the SD_VSEL into account to determine which
configuration register is used for the voltage setting.

Even without this change there is no functional issue, as the code
for switching the voltage in sdhci.c currently switches both, the
VSELECT/SD_VSEL signal and the regulator voltage at the same time
and doesn't run into an invalid corner case.

We should still make sure, that we always use the correct register
when controlling the regulator. At least in U-Boot this fixes an
actual bug where the wrong IO voltage is used and it makes sure
that the correct voltage can be read from sysfs.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts
index a8ef4fba16a9e185776da2fcc961bca45f3f9e53..d16490d876874b7bfc9066efdd724bbb52f518b7 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts
@@ -254,6 +254,10 @@
        status = "okay";
 };
 
+&reg_nvcc_sd {
+       sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+};
+
 &uart1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_uart1>;
@@ -454,7 +458,7 @@
                        MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2             0x1d0
                        MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3             0x1d0
                        MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12                0x19
-                       MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0xd0
+                       MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0x40000d0
                >;
        };
 
@@ -467,7 +471,7 @@
                        MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2             0x1d4
                        MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3             0x1d4
                        MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12                0x19
-                       MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0xd0
+                       MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0x40000d0
                >;
        };
 
@@ -480,7 +484,7 @@
                        MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2             0x1d6
                        MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3             0x1d6
                        MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12                0x19
-                       MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0xd0
+                       MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0x40000d0
                >;
        };
 };

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi
index 663ae52b48526e88dd71c8ca6081af6a97bcf462..d4554296523058b7230e826c72680b0a416bc316 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi
@@ -342,6 +342,7 @@
                                regulator-name = "NVCC_SD (LDO5)";
                                regulator-min-microvolt = <1800000>;
                                regulator-max-microvolt = <3300000>;
+                               sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
                        };
                };
        };
@@ -794,7 +795,7 @@
                        MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2             0x1d0 /* SDIO_A_D2 */
                        MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3             0x1d0 /* SDIO_A_D3 */
                        MX8MM_IOMUXC_SD2_WP_USDHC2_WP                   0x400000d6 /* SDIO_A_WP */
-                       MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0x90
+                       MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0x40000090
                >;
        };
 
@@ -807,7 +808,7 @@
                        MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2             0x1d4 /* SDIO_A_D2 */
                        MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3             0x1d4 /* SDIO_A_D3 */
                        MX8MM_IOMUXC_SD2_WP_USDHC2_WP                   0x400000d6 /* SDIO_A_WP */
-                       MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0x90
+                       MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0x40000090
                >;
        };
 
@@ -820,7 +821,7 @@
                        MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2             0x1d6 /* SDIO_A_D2 */
                        MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3             0x1d6 /* SDIO_A_D3 */
                        MX8MM_IOMUXC_SD2_WP_USDHC2_WP                   0x400000d6 /* SDIO_A_WP */
-                       MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0x90
+                       MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0x40000090
                >;
        };