/*
* Core driver for the S32 CC (Common Chassis) pin controller
*
- * Copyright 2017-2022 NXP
+ * Copyright 2017-2022,2024 NXP
* Copyright (C) 2022 SUSE LLC
* Copyright 2015-2016 Freescale Semiconductor, Inc.
*/
unsigned int offset,
bool input)
{
- unsigned int config;
+ /* Always enable IBE for GPIOs. This allows us to read the
+ * actual line value and compare it with the one set.
+ */
+ unsigned int config = S32_MSCR_IBE;
unsigned int mask = S32_MSCR_IBE | S32_MSCR_OBE;
- if (input) {
- /* Disable output buffer and enable input buffer */
- config = S32_MSCR_IBE;
- } else {
- /* Disable input buffer and enable output buffer */
- config = S32_MSCR_OBE;
- }
+ /* Enable output buffer */
+ if (!input)
+ config |= S32_MSCR_OBE;
return s32_regmap_update(pctldev, offset, mask, config);
}