drm/amdgpu: remove mdelay in psp v12

Since secure firmware is more stable than bring up phase, I believe we
don't need such mdelays any more before wait PSP response on PSP v12.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Trigger Huang <Trigger.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
index fcd708eae75ccef31f0f5d9fe472ddc331c4ebe9..6331941440d968a8a03339544824878b9260751c 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
@@ -99,9 +99,6 @@ static int psp_v12_0_bootloader_load_sysdrv(struct psp_context *psp)
        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
               psp_gfxdrv_command_reg);
 
-       /* there might be handshake issue with hardware which needs delay */
-       mdelay(20);
-
        ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
                           0x80000000, 0x80000000, false);
 
@@ -138,8 +135,6 @@ static int psp_v12_0_bootloader_load_sos(struct psp_context *psp)
        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
               psp_gfxdrv_command_reg);
 
-       /* there might be handshake issue with hardware which needs delay */
-       mdelay(20);
        ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
                           RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
                           0, true);
@@ -161,7 +156,6 @@ static void psp_v12_0_reroute_ih(struct psp_context *psp)
        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
 
-       mdelay(20);
        psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
                     0x80000000, 0x8000FFFF, false);
 
@@ -173,7 +167,6 @@ static void psp_v12_0_reroute_ih(struct psp_context *psp)
        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
 
-       mdelay(20);
        psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
                     0x80000000, 0x8000FFFF, false);
 }
@@ -200,9 +193,6 @@ static int psp_v12_0_ring_create(struct psp_context *psp,
                WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
                                             GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
 
-               /* there might be handshake issue with hardware which needs delay */
-               mdelay(20);
-
                /* Wait for response flag (bit 31) in C2PMSG_101 */
                ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
                                   0x80000000, 0x8000FFFF, false);
@@ -222,9 +212,6 @@ static int psp_v12_0_ring_create(struct psp_context *psp,
                psp_ring_reg = psp_ring_reg << 16;
                WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
 
-               /* there might be handshake issue with hardware which needs delay */
-               mdelay(20);
-
                /* Wait for response flag (bit 31) in C2PMSG_64 */
                ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
                                   0x80000000, 0x8000FFFF, false);
@@ -247,9 +234,6 @@ static int psp_v12_0_ring_stop(struct psp_context *psp,
                WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
                                     GFX_CTRL_CMD_ID_DESTROY_RINGS);
 
-       /* there might be handshake issue with hardware which needs delay */
-       mdelay(20);
-
        /* Wait for response flag (bit 31) */
        if (amdgpu_sriov_vf(adev))
                ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),