Merge drm/drm-next into drm-intel-next
authorJani Nikula <jani.nikula@intel.com>
Mon, 11 Apr 2022 13:01:56 +0000 (16:01 +0300)
committerJani Nikula <jani.nikula@intel.com>
Mon, 11 Apr 2022 13:01:56 +0000 (16:01 +0300)
Sync up with v5.18-rc1, in particular to get 5e3094cfd9fb
("drm/i915/xehpsdv: Add has_flat_ccs to device info").

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
31 files changed:
1  2 
drivers/gpu/drm/dp/drm_dp.c
drivers/gpu/drm/i915/Makefile
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
drivers/gpu/drm/i915/gem/i915_gem_context.c
drivers/gpu/drm/i915/gem/i915_gem_object.c
drivers/gpu/drm/i915/gem/i915_gem_region.c
drivers/gpu/drm/i915/gem/i915_gem_shmem.c
drivers/gpu/drm/i915/gem/i915_gem_stolen.c
drivers/gpu/drm/i915/gem/selftests/huge_pages.c
drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
drivers/gpu/drm/i915/gt/intel_engine_cs.c
drivers/gpu/drm/i915/gt/intel_execlists_submission.c
drivers/gpu/drm/i915/gt/intel_gt_regs.h
drivers/gpu/drm/i915/gt/intel_gtt.c
drivers/gpu/drm/i915/gt/intel_gtt.h
drivers/gpu/drm/i915/gt/intel_rps.c
drivers/gpu/drm/i915/gt/intel_sseu.c
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
drivers/gpu/drm/i915/i915_driver.c
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/i915_params.c
drivers/gpu/drm/i915/i915_pci.c
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_device_info.c
drivers/gpu/drm/i915/intel_device_info.h
drivers/gpu/drm/i915/intel_memory_region.c
drivers/gpu/drm/i915/intel_memory_region.h
drivers/gpu/drm/i915/intel_step.c
drivers/iommu/intel/iommu.c
include/drm/dp/drm_dp_helper.h

Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
index 8e321d300e0cd23f0f80449ef1cfaab941076ba5,c32c0c6661c898b6cfa8a05124a25fdffde695e0..9e077929ed671a0ef1a160087951065858c527d6
@@@ -1038,35 -1040,25 +1040,36 @@@ static const struct intel_device_info x
        .require_force_probe = 1,
  };
  
 +#define DG2_FEATURES \
 +      XE_HP_FEATURES, \
 +      XE_HPM_FEATURES, \
 +      DGFX_FEATURES, \
 +      .graphics.rel = 55, \
 +      .media.rel = 55, \
 +      PLATFORM(INTEL_DG2), \
 +      .has_4tile = 1, \
 +      .has_64k_pages = 1, \
 +      .has_guc_deprivilege = 1, \
++      .needs_compact_pt = 1, \
 +      .platform_engine_mask = \
 +              BIT(RCS0) | BIT(BCS0) | \
 +              BIT(VECS0) | BIT(VECS1) | \
 +              BIT(VCS0) | BIT(VCS2)
 +
  __maybe_unused
  static const struct intel_device_info dg2_info = {
 -      XE_HP_FEATURES,
 -      XE_HPM_FEATURES,
 +      DG2_FEATURES,
        XE_LPD_FEATURES,
 -      DGFX_FEATURES,
 -      .graphics.rel = 55,
 -      .media.rel = 55,
 -      PLATFORM(INTEL_DG2),
 -      .has_guc_deprivilege = 1,
 -      .has_64k_pages = 1,
 -      .needs_compact_pt = 1,
 -      .platform_engine_mask =
 -              BIT(RCS0) | BIT(BCS0) |
 -              BIT(VECS0) | BIT(VECS1) |
 -              BIT(VCS0) | BIT(VCS2),
 -      .require_force_probe = 1,
        .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
                               BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
 +      .require_force_probe = 1,
 +};
 +
 +__maybe_unused
 +static const struct intel_device_info ats_m_info = {
 +      DG2_FEATURES,
 +      .display = { 0 },
 +      .require_force_probe = 1,
  };
  
  #undef PLATFORM
Simple merge
index 8026e805ff12b6369f8894b4468190991a74151f,291215d9da282a4438d9887a65492e445a2e7107..f9b955810593bac47ec4ca390e9480cb9b1eeeb8
@@@ -131,9 -134,10 +134,11 @@@ enum intel_ppgtt_type 
        /* Keep has_* in alphabetical order */ \
        func(has_64bit_reloc); \
        func(has_64k_pages); \
+       func(needs_compact_pt); \
        func(gpu_reset_clobbers_display); \
        func(has_reset_engine); \
 +      func(has_4tile); \
+       func(has_flat_ccs); \
        func(has_global_mocs); \
        func(has_gt_uc); \
        func(has_guc_deprivilege); \
Simple merge
Simple merge
Simple merge