drm/rockchip: vop2: Remove AFBC from TRANSFORM_OFFSET register macro

This TRANSFORM_OFFSET register needs to be configured not only in
AFBC mode, but also in tile mode, so remove the AFBC/AFBCD prefix.

This also help avoid "exceeds 100 columns" warning from checkpatch.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20250218112744.34433-3-andyshrk@163.com

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
index b84e92a9a25a3c64e8cd230f2701ee21a4d3fbe3..d0cfde532f0e40feb06bcbe03e141fe1a133d9a2 100644 (file)
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
@@ -1525,7 +1525,7 @@ static void vop2_plane_atomic_update(struct drm_plane *plane,
                transform_offset = vop2_afbc_transform_offset(pstate, half_block_en);
                vop2_win_write(win, VOP2_WIN_AFBC_HDR_PTR, yrgb_mst);
                vop2_win_write(win, VOP2_WIN_AFBC_PIC_SIZE, act_info);
-               vop2_win_write(win, VOP2_WIN_AFBC_TRANSFORM_OFFSET, transform_offset);
+               vop2_win_write(win, VOP2_WIN_TRANSFORM_OFFSET, transform_offset);
                vop2_win_write(win, VOP2_WIN_AFBC_PIC_OFFSET, ((src->x1 >> 16) | src->y1));
                vop2_win_write(win, VOP2_WIN_AFBC_DSP_OFFSET, (dest->x1 | (dest->y1 << 16)));
                vop2_win_write(win, VOP2_WIN_AFBC_PIC_VIR_WIDTH, stride);
@@ -1536,7 +1536,7 @@ static void vop2_plane_atomic_update(struct drm_plane *plane,
        } else {
                if (vop2_cluster_window(win)) {
                        vop2_win_write(win, VOP2_WIN_AFBC_ENABLE, 0);
-                       vop2_win_write(win, VOP2_WIN_AFBC_TRANSFORM_OFFSET, 0);
+                       vop2_win_write(win, VOP2_WIN_TRANSFORM_OFFSET, 0);
                }
 
                vop2_win_write(win, VOP2_WIN_YRGB_VIR, DIV_ROUND_UP(fb->pitches[0], 4));
@@ -3460,7 +3460,7 @@ static const struct reg_field vop2_cluster_regs[VOP2_WIN_MAX_REG] = {
        [VOP2_WIN_AFBC_TILE_NUM] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH, 16, 31),
        [VOP2_WIN_AFBC_PIC_OFFSET] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_PIC_OFFSET, 0, 31),
        [VOP2_WIN_AFBC_DSP_OFFSET] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_DSP_OFFSET, 0, 31),
-       [VOP2_WIN_AFBC_TRANSFORM_OFFSET] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_TRANSFORM_OFFSET, 0, 31),
+       [VOP2_WIN_TRANSFORM_OFFSET] = REG_FIELD(RK3568_CLUSTER_WIN_TRANSFORM_OFFSET, 0, 31),
        [VOP2_WIN_AFBC_ROTATE_90] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 0, 0),
        [VOP2_WIN_AFBC_ROTATE_270] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 1, 1),
        [VOP2_WIN_XMIRROR] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 2, 2),
@@ -3559,7 +3559,7 @@ static const struct reg_field vop2_esmart_regs[VOP2_WIN_MAX_REG] = {
        [VOP2_WIN_AFBC_PIC_OFFSET] = { .reg = 0xffffffff },
        [VOP2_WIN_AFBC_PIC_SIZE] = { .reg = 0xffffffff },
        [VOP2_WIN_AFBC_DSP_OFFSET] = { .reg = 0xffffffff },
-       [VOP2_WIN_AFBC_TRANSFORM_OFFSET] = { .reg = 0xffffffff },
+       [VOP2_WIN_TRANSFORM_OFFSET] = { .reg = 0xffffffff },
        [VOP2_WIN_AFBC_HDR_PTR] = { .reg = 0xffffffff },
        [VOP2_WIN_AFBC_HALF_BLOCK_EN] = { .reg = 0xffffffff },
        [VOP2_WIN_AFBC_ROTATE_270] = { .reg = 0xffffffff },

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h
index 29cc7fb8f6d81d71b466b814b4ce3f566cafd173..156a272480f36872fb8bdeeafcf833a32bb0927b 100644 (file)
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h
@@ -118,7 +118,7 @@ enum vop2_win_regs {
        VOP2_WIN_AFBC_PIC_OFFSET,
        VOP2_WIN_AFBC_PIC_SIZE,
        VOP2_WIN_AFBC_DSP_OFFSET,
-       VOP2_WIN_AFBC_TRANSFORM_OFFSET,
+       VOP2_WIN_TRANSFORM_OFFSET,
        VOP2_WIN_AFBC_HDR_PTR,
        VOP2_WIN_AFBC_HALF_BLOCK_EN,
        VOP2_WIN_AFBC_ROTATE_270,
@@ -335,7 +335,7 @@ enum dst_factor_mode {
 #define RK3568_CLUSTER_WIN_DSP_INFO            0x24
 #define RK3568_CLUSTER_WIN_DSP_ST              0x28
 #define RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB     0x30
-#define RK3568_CLUSTER_WIN_AFBCD_TRANSFORM_OFFSET      0x3C
+#define RK3568_CLUSTER_WIN_TRANSFORM_OFFSET    0x3C
 #define RK3568_CLUSTER_WIN_AFBCD_OUTPUT_CTRL   0x50
 #define RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE   0x54
 #define RK3568_CLUSTER_WIN_AFBCD_HDR_PTR       0x58