rtw89: 8852c: add write/read crystal function in CFO tracking

The CFO tracking algorithm is the same, but control methods are different.
Set parameters via xtal serial interfaces (SI).

Signed-off-by: Yuan-Han Zhang <yuanhan1020@realtek.com>
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220317055543.40514-3-pkshih@realtek.com

diff --git a/drivers/net/wireless/realtek/rtw89/mac.h b/drivers/net/wireless/realtek/rtw89/mac.h
index 2f707c817fa797b299b4f8584c1ba01ad27c2239..680b0eea3174628354d921e0b7d5a16247ddfe5d 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/mac.h
+++ b/drivers/net/wireless/realtek/rtw89/mac.h
@@ -884,7 +884,9 @@ int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev,
 
 enum rtw89_mac_xtal_si_offset {
        XTAL_SI_XTAL_SC_XI = 0x04,
+#define XTAL_SC_XI_MASK                GENMASK(7, 0)
        XTAL_SI_XTAL_SC_XO = 0x05,
+#define XTAL_SC_XO_MASK                GENMASK(7, 0)
        XTAL_SI_PWR_CUT = 0x10,
 #define XTAL_SI_SMALL_PWR_CUT  BIT(0)
 #define XTAL_SI_BIG_PWR_CUT    BIT(1)

diff --git a/drivers/net/wireless/realtek/rtw89/phy.c b/drivers/net/wireless/realtek/rtw89/phy.c
index 6a7e08bdd00e7068b5547c42bc182446f161fb00..b75d08697a22467a84a2ac068e5456d3eb4d7397 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/phy.c
+++ b/drivers/net/wireless/realtek/rtw89/phy.c
@@ -4,6 +4,7 @@
 
 #include "debug.h"
 #include "fw.h"
+#include "mac.h"
 #include "phy.h"
 #include "ps.h"
 #include "reg.h"
@@ -1667,15 +1668,25 @@ static void rtw89_phy_cfo_set_crystal_cap(struct rtw89_dev *rtwdev,
                                          u8 crystal_cap, bool force)
 {
        struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
+       const struct rtw89_chip_info *chip = rtwdev->chip;
        u8 sc_xi_val, sc_xo_val;
 
        if (!force && cfo->crystal_cap == crystal_cap)
                return;
        crystal_cap = clamp_t(u8, crystal_cap, 0, 127);
-       rtw89_phy_cfo_set_xcap_reg(rtwdev, true, crystal_cap);
-       rtw89_phy_cfo_set_xcap_reg(rtwdev, false, crystal_cap);
-       sc_xo_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, true);
-       sc_xi_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, false);
+       if (chip->chip_id == RTL8852A) {
+               rtw89_phy_cfo_set_xcap_reg(rtwdev, true, crystal_cap);
+               rtw89_phy_cfo_set_xcap_reg(rtwdev, false, crystal_cap);
+               sc_xo_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, true);
+               sc_xi_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, false);
+       } else {
+               rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO,
+                                       crystal_cap, XTAL_SC_XO_MASK);
+               rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI,
+                                       crystal_cap, XTAL_SC_XI_MASK);
+               rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, &sc_xo_val);
+               rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, &sc_xi_val);
+       }
        cfo->crystal_cap = sc_xi_val;
        cfo->x_cap_ofst = (s8)((int)cfo->crystal_cap - cfo->def_x_cap);