clk: rockchip: rk3588: Add PLL rate for 1500 MHz

At least one RK3588 clock (CPLL) uses 1.5 GHz, so let's add
that frequency to the PLL table.

Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com>
Link: https://lore.kernel.org/r/20250408064612.41359-1-eagle.alexander923@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c
index 4031733def4e1ac0d842ab81e3bcd732772faf2e..1694223f4f842fb0099b42832055ea657551ebff 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3588.c
+++ b/drivers/clk/rockchip/clk-rk3588.c
@@ -64,6 +64,7 @@ static struct rockchip_pll_rate_table rk3588_pll_rates[] = {
        RK3588_PLL_RATE(1560000000, 2, 260, 1, 0),
        RK3588_PLL_RATE(1536000000, 2, 256, 1, 0),
        RK3588_PLL_RATE(1512000000, 2, 252, 1, 0),
+       RK3588_PLL_RATE(1500000000, 2, 250, 1, 0),
        RK3588_PLL_RATE(1488000000, 2, 248, 1, 0),
        RK3588_PLL_RATE(1464000000, 2, 244, 1, 0),
        RK3588_PLL_RATE(1440000000, 2, 240, 1, 0),