drm/nouveau/mmu: bump up the maximum page table depth
authorBen Skeggs <bskeggs@nvidia.com>
Wed, 12 Feb 2025 21:42:28 +0000 (07:42 +1000)
committerDave Airlie <airlied@redhat.com>
Sun, 18 May 2025 20:29:26 +0000 (06:29 +1000)
GH100/GBxxx have 6-level page tables.

Signed-off-by: Ben Skeggs <bskeggs@nvidia.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Timur Tabi <ttabi@nvidia.com>
Tested-by: Timur Tabi <ttabi@nvidia.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c

index 935b1cacd528e8416259803c533d4988004cc59f..7188e3eb2d07a1aefec583021d39837b55591d2f 100644 (file)
@@ -8,7 +8,7 @@ struct nvkm_vma {
        struct list_head head;
        struct rb_node tree;
        u64 addr;
-       u64 size:50;
+       u64 size;
        bool mapref:1; /* PTs (de)referenced on (un)map (vs pre-allocated). */
        bool sparse:1; /* Unmapped PDEs/PTEs will not trigger MMU faults. */
 #define NVKM_VMA_PAGE_NONE 7
index 9c97800fe03777e27fe9926b1bc9c86041843a94..b54397e5364c4fc637131f3d1f6cc9753bd96a47 100644 (file)
@@ -19,7 +19,7 @@
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
  */
-#define NVKM_VMM_LEVELS_MAX 5
+#define NVKM_VMM_LEVELS_MAX 6
 #include "vmm.h"
 
 #include <subdev/fb.h>