arm64: dts: qcom: qcs615: Add CPU capacity and DPC properties

Add "capacity-dmips-mhz" and "dynamic-power-coefficient" to the QCS615 SoC.
They are used to build the energy model, which in turn is used by EAS to
take placement decisions.

Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241211-add_cpu_capacity_and_dpc_properties-v1-1-03aaee023a77@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
index a1d75d8cb39ef1f64fd830e8100aef9f94148026..02425c78f50c1805a694ba9d420af1865be5af56 100644 (file)
--- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
@@ -29,6 +29,8 @@
                        enable-method = "psci";
                        power-domains = <&cpu_pd0>;
                        power-domain-names = "psci";
+                       capacity-dmips-mhz = <1024>;
+                       dynamic-power-coefficient = <100>;
                        next-level-cache = <&l2_0>;
                        #cooling-cells = <2>;
 
@@ -47,6 +49,8 @@
                        enable-method = "psci";
                        power-domains = <&cpu_pd1>;
                        power-domain-names = "psci";
+                       capacity-dmips-mhz = <1024>;
+                       dynamic-power-coefficient = <100>;
                        next-level-cache = <&l2_100>;
 
                        l2_100: l2-cache {
@@ -64,6 +68,8 @@
                        enable-method = "psci";
                        power-domains = <&cpu_pd2>;
                        power-domain-names = "psci";
+                       capacity-dmips-mhz = <1024>;
+                       dynamic-power-coefficient = <100>;
                        next-level-cache = <&l2_200>;
 
                        l2_200: l2-cache {
@@ -81,6 +87,8 @@
                        enable-method = "psci";
                        power-domains = <&cpu_pd3>;
                        power-domain-names = "psci";
+                       capacity-dmips-mhz = <1024>;
+                       dynamic-power-coefficient = <100>;
                        next-level-cache = <&l2_300>;
 
                        l2_300: l2-cache {
@@ -98,6 +106,8 @@
                        enable-method = "psci";
                        power-domains = <&cpu_pd4>;
                        power-domain-names = "psci";
+                       capacity-dmips-mhz = <1024>;
+                       dynamic-power-coefficient = <100>;
                        next-level-cache = <&l2_400>;
 
                        l2_400: l2-cache {
@@ -115,6 +125,8 @@
                        enable-method = "psci";
                        power-domains = <&cpu_pd5>;
                        power-domain-names = "psci";
+                       capacity-dmips-mhz = <1024>;
+                       dynamic-power-coefficient = <100>;
                        next-level-cache = <&l2_500>;
 
                        l2_500: l2-cache {
@@ -132,6 +144,8 @@
                        enable-method = "psci";
                        power-domains = <&cpu_pd6>;
                        power-domain-names = "psci";
+                       capacity-dmips-mhz = <1740>;
+                       dynamic-power-coefficient = <404>;
                        next-level-cache = <&l2_600>;
                        #cooling-cells = <2>;
 
@@ -150,6 +164,8 @@
                        enable-method = "psci";
                        power-domains = <&cpu_pd7>;
                        power-domain-names = "psci";
+                       capacity-dmips-mhz = <1740>;
+                       dynamic-power-coefficient = <404>;
                        next-level-cache = <&l2_700>;
 
                        l2_700: l2-cache {