ARM: tegra: Fix missed EMC registers latching on resume from LP1 on Tegra30+

The memory interface configuration and re-calibration interval are left
unassigned on resume from LP1 because these registers are shadowed and
require latching after being adjusted.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index dd4a67dabd91692dffae18fd07245c372770840f..efc6493b61f3ad9b275b927dc04c55aab078b4cf 100644 (file)
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -521,6 +521,8 @@ zcal_done:
        ldr     r1, [r5, #0x0]          @ restore EMC_CFG
        str     r1, [r0, #EMC_CFG]
 
+       emc_timing_update r1, r0
+
        /* Tegra114 had dual EMC channel, now config the other one */
        cmp     r10, #TEGRA114
        bne     __no_dual_emc_chanl