drm/amd/display: Remove useless comparison of unsigned int vs. 0
authorAlex Hung <alex.hung@amd.com>
Wed, 29 May 2024 23:50:44 +0000 (17:50 -0600)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 14 Jun 2024 20:17:17 +0000 (16:17 -0400)
[WHY & HOW]
The comparisons of unsigned int with 0 can have no meanings, i.e.
unsigned int >= 0 (always true) or unsigned int < 0 (always false), and
therefore they are removed.

This fixes 12 NO_EFFECT issues reported by Coverity.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.c
drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c
drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c
drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c
drivers/gpu/drm/amd/display/dc/irq/irq_service.c

index aea4bb46856eff15fe8684281853fa09a5ec231a..a650a9877097bd183dbe1005a759406ba8d08deb 100644 (file)
@@ -320,16 +320,16 @@ static void rn_dump_clk_registers(struct clk_state_registers_and_bypass *regs_an
        regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10;
 
        regs_and_bypass->dppclk_bypass = internal.CLK1_CLK1_BYPASS_CNTL & 0x0007;
-       if (regs_and_bypass->dppclk_bypass < 0 || regs_and_bypass->dppclk_bypass > 4)
+       if (regs_and_bypass->dppclk_bypass > 4)
                regs_and_bypass->dppclk_bypass = 0;
        regs_and_bypass->dcfclk_bypass = internal.CLK1_CLK3_BYPASS_CNTL & 0x0007;
-       if (regs_and_bypass->dcfclk_bypass < 0 || regs_and_bypass->dcfclk_bypass > 4)
+       if (regs_and_bypass->dcfclk_bypass > 4)
                regs_and_bypass->dcfclk_bypass = 0;
        regs_and_bypass->dispclk_bypass = internal.CLK1_CLK0_BYPASS_CNTL & 0x0007;
-       if (regs_and_bypass->dispclk_bypass < 0 || regs_and_bypass->dispclk_bypass > 4)
+       if (regs_and_bypass->dispclk_bypass > 4)
                regs_and_bypass->dispclk_bypass = 0;
        regs_and_bypass->dprefclk_bypass = internal.CLK1_CLK2_BYPASS_CNTL & 0x0007;
-       if (regs_and_bypass->dprefclk_bypass < 0 || regs_and_bypass->dprefclk_bypass > 4)
+       if (regs_and_bypass->dprefclk_bypass > 4)
                regs_and_bypass->dprefclk_bypass = 0;
 
        if (log_info->enabled) {
index 191d8b969d19a6e38eb082252f5a67955659bf9e..148a0e4cdea25a7d5aca8b5621909e69e548834e 100644 (file)
@@ -252,16 +252,16 @@ static void vg_dump_clk_registers(struct clk_state_registers_and_bypass *regs_an
        regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10;
 
        regs_and_bypass->dppclk_bypass = internal.CLK1_CLK1_BYPASS_CNTL & 0x0007;
-       if (regs_and_bypass->dppclk_bypass < 0 || regs_and_bypass->dppclk_bypass > 4)
+       if (regs_and_bypass->dppclk_bypass > 4)
                regs_and_bypass->dppclk_bypass = 0;
        regs_and_bypass->dcfclk_bypass = internal.CLK1_CLK3_BYPASS_CNTL & 0x0007;
-       if (regs_and_bypass->dcfclk_bypass < 0 || regs_and_bypass->dcfclk_bypass > 4)
+       if (regs_and_bypass->dcfclk_bypass > 4)
                regs_and_bypass->dcfclk_bypass = 0;
        regs_and_bypass->dispclk_bypass = internal.CLK1_CLK0_BYPASS_CNTL & 0x0007;
-       if (regs_and_bypass->dispclk_bypass < 0 || regs_and_bypass->dispclk_bypass > 4)
+       if (regs_and_bypass->dispclk_bypass > 4)
                regs_and_bypass->dispclk_bypass = 0;
        regs_and_bypass->dprefclk_bypass = internal.CLK1_CLK2_BYPASS_CNTL & 0x0007;
-       if (regs_and_bypass->dprefclk_bypass < 0 || regs_and_bypass->dprefclk_bypass > 4)
+       if (regs_and_bypass->dprefclk_bypass > 4)
                regs_and_bypass->dprefclk_bypass = 0;
 
        if (log_info->enabled) {
index 4cdd4dacb7618663dc979ae3e888e98bf97f69d7..f5e1d9caee4c822255b14d1b44970568aa72882f 100644 (file)
@@ -642,8 +642,7 @@ static void dce_mi_program_surface_config(
        program_tiling(dce_mi, tiling_info);
        program_size_and_rotation(dce_mi, rotation, plane_size);
 
-       if (format >= SURFACE_PIXEL_FORMAT_GRPH_BEGIN &&
-               format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
+       if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
                program_grph_pixel_format(dce_mi, format);
 }
 
@@ -663,8 +662,7 @@ static void dce60_mi_program_surface_config(
        program_tiling(dce_mi, tiling_info);
        dce60_program_size(dce_mi, rotation, plane_size);
 
-       if (format >= SURFACE_PIXEL_FORMAT_GRPH_BEGIN &&
-               format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
+       if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
                program_grph_pixel_format(dce_mi, format);
 }
 #endif
index 53bd0ae4bab5ed0d473dc5cee57668c8c475fa2a..af21c0a27f86571311f4e7467e88d9d87688cb84 100644 (file)
@@ -359,7 +359,7 @@ void pg_cntl35_mpcc_pg_control(struct pg_cntl *pg_cntl,
        if (pg_cntl->ctx->dc->idle_optimizations_allowed)
                return;
 
-       if (mpcc_inst >= 0 && mpcc_inst < MAX_PIPES)
+       if (mpcc_inst < MAX_PIPES)
                pg_cntl->pg_pipe_res_enable[PG_MPCC][mpcc_inst] = power_on;
 }
 
@@ -369,7 +369,7 @@ void pg_cntl35_opp_pg_control(struct pg_cntl *pg_cntl,
        if (pg_cntl->ctx->dc->idle_optimizations_allowed)
                return;
 
-       if (opp_inst >= 0 && opp_inst < MAX_PIPES)
+       if (opp_inst < MAX_PIPES)
                pg_cntl->pg_pipe_res_enable[PG_OPP][opp_inst] = power_on;
 }
 
@@ -379,7 +379,7 @@ void pg_cntl35_optc_pg_control(struct pg_cntl *pg_cntl,
        if (pg_cntl->ctx->dc->idle_optimizations_allowed)
                return;
 
-       if (optc_inst >= 0 && optc_inst < MAX_PIPES)
+       if (optc_inst < MAX_PIPES)
                pg_cntl->pg_pipe_res_enable[PG_OPTC][optc_inst] = power_on;
 }
 
index 525bc8881950d268a4534fe77f49312079aadbc3..d9e6e70dc394bdd7f1cf984aed3961f898ce031a 100644 (file)
@@ -170,8 +170,7 @@ static enum gpio_result set_config(
 
                return GPIO_RESULT_OK;
        case GPIO_DDC_CONFIG_TYPE_POLL_FOR_CONNECT:
-               if ((hw_gpio->base.en >= GPIO_DDC_LINE_DDC1) &&
-                       (hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA)) {
+               if (hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA) {
                        REG_UPDATE_3(ddc_setup,
                                DC_I2C_DDC1_ENABLE, 1,
                                DC_I2C_DDC1_EDID_DETECT_ENABLE, 1,
@@ -180,8 +179,7 @@ static enum gpio_result set_config(
                }
        break;
        case GPIO_DDC_CONFIG_TYPE_POLL_FOR_DISCONNECT:
-               if ((hw_gpio->base.en >= GPIO_DDC_LINE_DDC1) &&
-                       (hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA)) {
+               if (hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA) {
                        REG_UPDATE_3(ddc_setup,
                                DC_I2C_DDC1_ENABLE, 1,
                                DC_I2C_DDC1_EDID_DETECT_ENABLE, 1,
@@ -190,8 +188,7 @@ static enum gpio_result set_config(
                }
        break;
        case GPIO_DDC_CONFIG_TYPE_DISABLE_POLLING:
-               if ((hw_gpio->base.en >= GPIO_DDC_LINE_DDC1) &&
-                       (hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA)) {
+               if (hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA) {
                        REG_UPDATE_2(ddc_setup,
                                DC_I2C_DDC1_ENABLE, 0,
                                DC_I2C_DDC1_EDID_DETECT_ENABLE, 0);
@@ -231,7 +228,7 @@ void dal_hw_ddc_init(
        enum gpio_id id,
        uint32_t en)
 {
-       if ((en < GPIO_DDC_LINE_MIN) || (en > GPIO_DDC_LINE_MAX)) {
+       if (en > GPIO_DDC_LINE_MAX) {
                ASSERT_CRITICAL(false);
                *hw_ddc = NULL;
        }
index f9e847e6555d9b45547903bd1508daaee77df296..6cd50232c432907d91f59cf27b0b3c52e75bf962 100644 (file)
@@ -106,7 +106,7 @@ void dal_hw_generic_init(
        enum gpio_id id,
        uint32_t en)
 {
-       if ((en < GPIO_DDC_LINE_MIN) || (en > GPIO_DDC_LINE_MAX)) {
+       if (en > GPIO_DDC_LINE_MAX) {
                ASSERT_CRITICAL(false);
                *hw_generic = NULL;
        }
index 1489fdfaf0e7e5bb902fe9f6f911e02948b3908f..3f13a744d07da634ec02219aa70fa9cd99094274 100644 (file)
@@ -127,7 +127,7 @@ void dal_hw_hpd_init(
        enum gpio_id id,
        uint32_t en)
 {
-       if ((en < GPIO_DDC_LINE_MIN) || (en > GPIO_DDC_LINE_MAX)) {
+       if (en > GPIO_DDC_LINE_MAX) {
                ASSERT_CRITICAL(false);
                *hw_hpd = NULL;
        }
index d100edaedbbb815adec8a8e98ba9b52fb9188516..eca3d7ee7e4ed24d151e2e206321e43debd24bca 100644 (file)
@@ -76,7 +76,7 @@ static const struct irq_source_info *find_irq_source_info(
        struct irq_service *irq_service,
        enum dc_irq_source source)
 {
-       if (source >= DAL_IRQ_SOURCES_NUMBER || source < DC_IRQ_SOURCE_INVALID)
+       if (source >= DAL_IRQ_SOURCES_NUMBER)
                return NULL;
 
        return &irq_service->info[source];