regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10;
regs_and_bypass->dppclk_bypass = internal.CLK1_CLK1_BYPASS_CNTL & 0x0007;
- if (regs_and_bypass->dppclk_bypass < 0 || regs_and_bypass->dppclk_bypass > 4)
+ if (regs_and_bypass->dppclk_bypass > 4)
regs_and_bypass->dppclk_bypass = 0;
regs_and_bypass->dcfclk_bypass = internal.CLK1_CLK3_BYPASS_CNTL & 0x0007;
- if (regs_and_bypass->dcfclk_bypass < 0 || regs_and_bypass->dcfclk_bypass > 4)
+ if (regs_and_bypass->dcfclk_bypass > 4)
regs_and_bypass->dcfclk_bypass = 0;
regs_and_bypass->dispclk_bypass = internal.CLK1_CLK0_BYPASS_CNTL & 0x0007;
- if (regs_and_bypass->dispclk_bypass < 0 || regs_and_bypass->dispclk_bypass > 4)
+ if (regs_and_bypass->dispclk_bypass > 4)
regs_and_bypass->dispclk_bypass = 0;
regs_and_bypass->dprefclk_bypass = internal.CLK1_CLK2_BYPASS_CNTL & 0x0007;
- if (regs_and_bypass->dprefclk_bypass < 0 || regs_and_bypass->dprefclk_bypass > 4)
+ if (regs_and_bypass->dprefclk_bypass > 4)
regs_and_bypass->dprefclk_bypass = 0;
if (log_info->enabled) {
regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10;
regs_and_bypass->dppclk_bypass = internal.CLK1_CLK1_BYPASS_CNTL & 0x0007;
- if (regs_and_bypass->dppclk_bypass < 0 || regs_and_bypass->dppclk_bypass > 4)
+ if (regs_and_bypass->dppclk_bypass > 4)
regs_and_bypass->dppclk_bypass = 0;
regs_and_bypass->dcfclk_bypass = internal.CLK1_CLK3_BYPASS_CNTL & 0x0007;
- if (regs_and_bypass->dcfclk_bypass < 0 || regs_and_bypass->dcfclk_bypass > 4)
+ if (regs_and_bypass->dcfclk_bypass > 4)
regs_and_bypass->dcfclk_bypass = 0;
regs_and_bypass->dispclk_bypass = internal.CLK1_CLK0_BYPASS_CNTL & 0x0007;
- if (regs_and_bypass->dispclk_bypass < 0 || regs_and_bypass->dispclk_bypass > 4)
+ if (regs_and_bypass->dispclk_bypass > 4)
regs_and_bypass->dispclk_bypass = 0;
regs_and_bypass->dprefclk_bypass = internal.CLK1_CLK2_BYPASS_CNTL & 0x0007;
- if (regs_and_bypass->dprefclk_bypass < 0 || regs_and_bypass->dprefclk_bypass > 4)
+ if (regs_and_bypass->dprefclk_bypass > 4)
regs_and_bypass->dprefclk_bypass = 0;
if (log_info->enabled) {
program_tiling(dce_mi, tiling_info);
program_size_and_rotation(dce_mi, rotation, plane_size);
- if (format >= SURFACE_PIXEL_FORMAT_GRPH_BEGIN &&
- format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
+ if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
program_grph_pixel_format(dce_mi, format);
}
program_tiling(dce_mi, tiling_info);
dce60_program_size(dce_mi, rotation, plane_size);
- if (format >= SURFACE_PIXEL_FORMAT_GRPH_BEGIN &&
- format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
+ if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
program_grph_pixel_format(dce_mi, format);
}
#endif
if (pg_cntl->ctx->dc->idle_optimizations_allowed)
return;
- if (mpcc_inst >= 0 && mpcc_inst < MAX_PIPES)
+ if (mpcc_inst < MAX_PIPES)
pg_cntl->pg_pipe_res_enable[PG_MPCC][mpcc_inst] = power_on;
}
if (pg_cntl->ctx->dc->idle_optimizations_allowed)
return;
- if (opp_inst >= 0 && opp_inst < MAX_PIPES)
+ if (opp_inst < MAX_PIPES)
pg_cntl->pg_pipe_res_enable[PG_OPP][opp_inst] = power_on;
}
if (pg_cntl->ctx->dc->idle_optimizations_allowed)
return;
- if (optc_inst >= 0 && optc_inst < MAX_PIPES)
+ if (optc_inst < MAX_PIPES)
pg_cntl->pg_pipe_res_enable[PG_OPTC][optc_inst] = power_on;
}
return GPIO_RESULT_OK;
case GPIO_DDC_CONFIG_TYPE_POLL_FOR_CONNECT:
- if ((hw_gpio->base.en >= GPIO_DDC_LINE_DDC1) &&
- (hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA)) {
+ if (hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA) {
REG_UPDATE_3(ddc_setup,
DC_I2C_DDC1_ENABLE, 1,
DC_I2C_DDC1_EDID_DETECT_ENABLE, 1,
}
break;
case GPIO_DDC_CONFIG_TYPE_POLL_FOR_DISCONNECT:
- if ((hw_gpio->base.en >= GPIO_DDC_LINE_DDC1) &&
- (hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA)) {
+ if (hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA) {
REG_UPDATE_3(ddc_setup,
DC_I2C_DDC1_ENABLE, 1,
DC_I2C_DDC1_EDID_DETECT_ENABLE, 1,
}
break;
case GPIO_DDC_CONFIG_TYPE_DISABLE_POLLING:
- if ((hw_gpio->base.en >= GPIO_DDC_LINE_DDC1) &&
- (hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA)) {
+ if (hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA) {
REG_UPDATE_2(ddc_setup,
DC_I2C_DDC1_ENABLE, 0,
DC_I2C_DDC1_EDID_DETECT_ENABLE, 0);
enum gpio_id id,
uint32_t en)
{
- if ((en < GPIO_DDC_LINE_MIN) || (en > GPIO_DDC_LINE_MAX)) {
+ if (en > GPIO_DDC_LINE_MAX) {
ASSERT_CRITICAL(false);
*hw_ddc = NULL;
}
enum gpio_id id,
uint32_t en)
{
- if ((en < GPIO_DDC_LINE_MIN) || (en > GPIO_DDC_LINE_MAX)) {
+ if (en > GPIO_DDC_LINE_MAX) {
ASSERT_CRITICAL(false);
*hw_generic = NULL;
}
enum gpio_id id,
uint32_t en)
{
- if ((en < GPIO_DDC_LINE_MIN) || (en > GPIO_DDC_LINE_MAX)) {
+ if (en > GPIO_DDC_LINE_MAX) {
ASSERT_CRITICAL(false);
*hw_hpd = NULL;
}
struct irq_service *irq_service,
enum dc_irq_source source)
{
- if (source >= DAL_IRQ_SOURCES_NUMBER || source < DC_IRQ_SOURCE_INVALID)
+ if (source >= DAL_IRQ_SOURCES_NUMBER)
return NULL;
return &irq_service->info[source];