void amdgpu_gfx_state_change_set(struct amdgpu_device *adev, enum gfx_change_state state)
{
-
- mutex_lock(&adev->pm.mutex);
-
- if (adev->powerplay.pp_funcs &&
- adev->powerplay.pp_funcs->gfx_state_change_set)
+ if (is_support_sw_smu(adev)) {
+ smu_gfx_state_change_set(&adev->smu, state);
+ } else {
+ mutex_lock(&adev->pm.mutex);
+ if (adev->powerplay.pp_funcs &&
+ adev->powerplay.pp_funcs->gfx_state_change_set)
((adev)->powerplay.pp_funcs->gfx_state_change_set(
- (adev)->powerplay.pp_handle, state));
-
- mutex_unlock(&adev->pm.mutex);
-
+ (adev)->powerplay.pp_handle, state));
+ mutex_unlock(&adev->pm.mutex);
+ }
}
int (*post_init)(struct smu_context *smu);
void (*interrupt_work)(struct smu_context *smu);
int (*gpo_control)(struct smu_context *smu, bool enablement);
+ int (*gfx_state_change_set)(struct smu_context *smu, uint32_t state);
};
typedef enum {
ssize_t smu_sys_get_gpu_metrics(struct smu_context *smu, void **table);
int smu_enable_mgpu_fan_boost(struct smu_context *smu);
+int smu_gfx_state_change_set(struct smu_context *smu, uint32_t state);
#endif
#endif
return ret;
}
+
+int smu_gfx_state_change_set(struct smu_context *smu, uint32_t state)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+ if (smu->ppt_funcs->gfx_state_change_set)
+ ret = smu->ppt_funcs->gfx_state_change_set(smu, state);
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
return sizeof(struct gpu_metrics_v2_0);
}
+static int renoir_gfx_state_change_set(struct smu_context *smu, uint32_t state)
+{
+
+ return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GpuChangeState, state, NULL);
+}
+
static const struct pptable_funcs renoir_ppt_funcs = {
.set_power_state = NULL,
.print_clk_levels = renoir_print_clk_levels,
.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
.set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
.get_gpu_metrics = renoir_get_gpu_metrics,
+ .gfx_state_change_set = renoir_gfx_state_change_set,
};
void renoir_set_ppt_funcs(struct smu_context *smu)