drm/amd/pm: add gfx_state_change_set() for rn gfx power switch (v2)
authorPrike Liang <Prike.Liang@amd.com>
Tue, 20 Oct 2020 07:58:30 +0000 (15:58 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 13 Nov 2020 22:29:45 +0000 (17:29 -0500)
The gfx_state_change_set() funtion can support set GFX power
change status to D0/D3.

v2: make sure to register callback (Alex)

Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

index 380dd3a1baf49ce7cdef360727d7e198d337dbca..cd2c676a2797cc084950f90a0727064c6e076181 100644 (file)
@@ -828,14 +828,14 @@ int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev)
 
 void amdgpu_gfx_state_change_set(struct amdgpu_device *adev, enum gfx_change_state state)
 {
-
-       mutex_lock(&adev->pm.mutex);
-
-       if (adev->powerplay.pp_funcs &&
-           adev->powerplay.pp_funcs->gfx_state_change_set)
+       if (is_support_sw_smu(adev)) {
+               smu_gfx_state_change_set(&adev->smu, state);
+       } else {
+               mutex_lock(&adev->pm.mutex);
+               if (adev->powerplay.pp_funcs &&
+                   adev->powerplay.pp_funcs->gfx_state_change_set)
                        ((adev)->powerplay.pp_funcs->gfx_state_change_set(
-                                       (adev)->powerplay.pp_handle, state));
-
-       mutex_unlock(&adev->pm.mutex);
-
+                               (adev)->powerplay.pp_handle, state));
+               mutex_unlock(&adev->pm.mutex);
+       }
 }
index 9724d6fd82f444c98994dddafe3cb1d0df1cb50b..ae8ff7b07932eb681fd8120aec602b17b728ee04 100644 (file)
@@ -576,6 +576,7 @@ struct pptable_funcs {
        int (*post_init)(struct smu_context *smu);
        void (*interrupt_work)(struct smu_context *smu);
        int (*gpo_control)(struct smu_context *smu, bool enablement);
+       int (*gfx_state_change_set)(struct smu_context *smu, uint32_t state);
 };
 
 typedef enum {
@@ -764,6 +765,7 @@ int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value);
 ssize_t smu_sys_get_gpu_metrics(struct smu_context *smu, void **table);
 
 int smu_enable_mgpu_fan_boost(struct smu_context *smu);
+int smu_gfx_state_change_set(struct smu_context *smu, uint32_t state);
 
 #endif
 #endif
index 39990790ed67687b4a481e495fc1f12746620c39..7b698c5ddad0d42999256642f205dbd3c3841226 100644 (file)
@@ -2529,3 +2529,15 @@ int smu_enable_mgpu_fan_boost(struct smu_context *smu)
 
        return ret;
 }
+
+int smu_gfx_state_change_set(struct smu_context *smu, uint32_t state)
+{
+       int ret = 0;
+
+       mutex_lock(&smu->mutex);
+       if (smu->ppt_funcs->gfx_state_change_set)
+               ret = smu->ppt_funcs->gfx_state_change_set(smu, state);
+       mutex_unlock(&smu->mutex);
+
+       return ret;
+}
index 66c1026489bee514f720020c972228cb3da77072..46c44f0abdfb83ffcc7a52708d35a98ff2c746c5 100644 (file)
@@ -1136,6 +1136,12 @@ static ssize_t renoir_get_gpu_metrics(struct smu_context *smu,
        return sizeof(struct gpu_metrics_v2_0);
 }
 
+static int renoir_gfx_state_change_set(struct smu_context *smu, uint32_t state)
+{
+
+       return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GpuChangeState, state, NULL);
+}
+
 static const struct pptable_funcs renoir_ppt_funcs = {
        .set_power_state = NULL,
        .print_clk_levels = renoir_print_clk_levels,
@@ -1171,6 +1177,7 @@ static const struct pptable_funcs renoir_ppt_funcs = {
        .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
        .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
        .get_gpu_metrics = renoir_get_gpu_metrics,
+       .gfx_state_change_set = renoir_gfx_state_change_set,
 };
 
 void renoir_set_ppt_funcs(struct smu_context *smu)