drm/i915: Track pipe csc enable in crtc state

Just like we did for pipe gamma, let's also track the pipe csc
state. The hardware only exists on ILK+, and currently we always
enable it on hsw+ and never on any other platforms. Just like
with pipe gamma, the primary plane control register is used
for the readout on pre-SKL, and the pipe bottom color register
on SKL+.

v2: Rebase
v3: Allow fastboot with csc_enable changes (Maarten)
    Deal with HAS_GMCH

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190207202146.26423-4-ville.syrjala@linux.intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c3bc99d9a9042cb639dbe645101df73719fc7ec0..11bf60d5e748ed69838d4938381dc84092c43a6a 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6130,7 +6130,7 @@ enum {
 #define   MCURSOR_PIPE_SELECT_SHIFT    28
 #define   MCURSOR_PIPE_SELECT(pipe)    ((pipe) << 28)
 #define   MCURSOR_GAMMA_ENABLE  (1 << 26)
-#define   MCURSOR_PIPE_CSC_ENABLE (1 << 24)
+#define   MCURSOR_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */
 #define   MCURSOR_ROTATE_180   (1 << 15)
 #define   MCURSOR_TRICKLE_FEED_DISABLE (1 << 14)
 #define _CURABASE              0x70084
@@ -6185,7 +6185,7 @@ enum {
 #define   DISPPLANE_RGBA888                    (0xf << 26)
 #define   DISPPLANE_STEREO_ENABLE              (1 << 25)
 #define   DISPPLANE_STEREO_DISABLE             0
-#define   DISPPLANE_PIPE_CSC_ENABLE            (1 << 24)
+#define   DISPPLANE_PIPE_CSC_ENABLE            (1 << 24) /* ilk+ */
 #define   DISPPLANE_SEL_PIPE_SHIFT             24
 #define   DISPPLANE_SEL_PIPE_MASK              (3 << DISPPLANE_SEL_PIPE_SHIFT)
 #define   DISPPLANE_SEL_PIPE(pipe)             ((pipe) << DISPPLANE_SEL_PIPE_SHIFT)

diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 746138d7bcbcfd6d900298b19694f2ba49d1293a..e3bf3bd355abe8e45602e3465629e355f8e0314c 100644 (file)
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -401,7 +401,8 @@ static void skl_color_commit(const struct intel_crtc_state *crtc_state)
         */
        if (crtc_state->gamma_enable)
                val |= SKL_BOTTOM_COLOR_GAMMA_ENABLE;
-       val |= SKL_BOTTOM_COLOR_CSC_ENABLE;
+       if (crtc_state->csc_enable)
+               val |= SKL_BOTTOM_COLOR_CSC_ENABLE;
        I915_WRITE(SKL_BOTTOM_COLOR(pipe), val);
 
        I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
@@ -668,6 +669,10 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
 
        crtc_state->gamma_enable = true;
 
+       if (INTEL_GEN(dev_priv) >= 9 ||
+           IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
+               crtc_state->csc_enable = true;
+
        /* Always allow legacy gamma LUT with no further checking. */
        if (crtc_state_is_legacy_gamma(crtc_state)) {
                crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6f5f7525a2cb02ba89b6288533295c00a9f67cfd..78f46a94733d57bdd442f4683915b6a5cce77744 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3224,7 +3224,7 @@ static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
        if (crtc_state->gamma_enable)
                dspcntr |= DISPPLANE_GAMMA_ENABLE;
 
-       if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
+       if (crtc_state->csc_enable)
                dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
 
        if (INTEL_GEN(dev_priv) < 5)
@@ -3705,7 +3705,8 @@ u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
        if (crtc_state->gamma_enable)
                plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
 
-       plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
+       if (crtc_state->csc_enable)
+               plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
 
        return plane_ctl;
 }
@@ -3760,7 +3761,8 @@ u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
        if (crtc_state->gamma_enable)
                plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
 
-       plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
+       if (crtc_state->csc_enable)
+               plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
 
        return plane_color_ctl;
 }
@@ -8108,6 +8110,10 @@ static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
 
        if (tmp & DISPPLANE_GAMMA_ENABLE)
                crtc_state->gamma_enable = true;
+
+       if (!HAS_GMCH(dev_priv) &&
+           tmp & DISPPLANE_PIPE_CSC_ENABLE)
+               crtc_state->csc_enable = true;
 }
 
 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
@@ -9879,6 +9885,9 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
 
                if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
                        pipe_config->gamma_enable = true;
+
+               if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
+                       pipe_config->csc_enable = true;
        } else {
                i9xx_get_pipe_color_config(pipe_config);
        }
@@ -10215,7 +10224,7 @@ static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
        if (crtc_state->gamma_enable)
                cntl = MCURSOR_GAMMA_ENABLE;
 
-       if (HAS_DDI(dev_priv))
+       if (crtc_state->csc_enable)
                cntl |= MCURSOR_PIPE_CSC_ENABLE;
 
        if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
@@ -12115,6 +12124,7 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv,
 
                PIPE_CONF_CHECK_X(gamma_mode);
                PIPE_CONF_CHECK_BOOL(gamma_enable);
+               PIPE_CONF_CHECK_BOOL(csc_enable);
        }
 
        PIPE_CONF_CHECK_BOOL(double_wide);

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 52584d9516d4dcddc89af7ccc39de46fa7d1d511..37e9542994d49b66bbcf25c789635ce56aaa1205 100644 (file)
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -963,6 +963,9 @@ struct intel_crtc_state {
        /* enable pipe gamma? */
        bool gamma_enable;
 
+       /* enable pipe csc? */
+       bool csc_enable;
+
        /* Display Stream compression state */
        struct {
                bool compression_enable;

diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index db373e3ac601def2531c71bfe7a01e20b1891271..610398607e8ea164262f8fed2343080ca0c66340 100644 (file)
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -921,13 +921,12 @@ vlv_plane_get_hw_state(struct intel_plane *plane,
 
 static u32 ivb_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
 {
-       struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
        u32 sprctl = 0;
 
        if (crtc_state->gamma_enable)
                sprctl |= SPRITE_GAMMA_ENABLE;
 
-       if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
+       if (crtc_state->csc_enable)
                sprctl |= SPRITE_PIPE_CSC_ENABLE;
 
        return sprctl;
@@ -1118,6 +1117,9 @@ static u32 g4x_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
        if (crtc_state->gamma_enable)
                dvscntr |= DVS_GAMMA_ENABLE;
 
+       if (crtc_state->csc_enable)
+               dvscntr |= DVS_PIPE_CSC_ENABLE;
+
        return dvscntr;
 }